Samsung RT55EANS Especificações descarregar pdf (Página 91)

Ref# 420826 Intel

Atom™ processor CE4100 91

Platform Design Guide

Intel Confidential

8.1.1.2 Serial ATA Trace Length Guidelines

Table 8-1. Serial ATA Differential Pair Routing Guidelines for the 1080 Stack-up

Parameter Routing Guidelines Figure

Signal Group SATA[0:1]_Txp, SATA[0:1]_Txn

SATA[0:1]_Rxp, SATA[0:1]_Rxn

Reference Plane Gnd Referenced,

Ground vias are required when signal net has layer transition.

Layer Assignment Micro Strip (top or bottom layer)

Trace Impedance (Z0) 100 Ω +/-10% (differential)

(nominal 55 Ω, if it is single-end)

nominal Trace width (W)4.0 mils –micro strip

Nominal Trace Spacing (S)Intra-pair Trace Spacing (fixed):7.0 mils - microstrip

(S1)Inter-pair spacing (minimum): 21 mils

(S2)To Other signal space (minimum): 21 mils

nominal Trace Length Keep all lengths as short as possible.

TL1: 0.1” to 0.5”

TLT=TL1+TL2 +TL3--- 2” to 6”.

Length Matching

requirements

Length matching over TLT within a differential is within 50 mils or

less.

Breakout 4 mils width with 14 mils inter-pair spacing up to 0.5”Minimize

breakout length.

Breakout length is included in TLT.

Vias Maximum 2 vias in each net.

Ground vias are required when signal net has layer transition

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