Samsung RT55EANS Especificações Página 129

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Ref# 420826 Intel
®
Atom™ processor CE4100 129
Platform Design Guide
Intel Confidential
9.2.2 HDVCAP Design Topology 2
Figure 9-3. HDVCAP Signal Topology With NAND Boot
Table 9-3. HDVCAP Signal Length Table
Traces Description Layer
Min
Length
Max
Length
Trace
Width
Spacing
TL1 SDV Breakout Micro strip 0.3” 0.7” 4 Mils >=4 Mils
TL2 +TL1 Lead-in Micro strip 1” 2.5” 4 Mils >=8Mils
Notes:
33 resistor should be close to HDMI Rx Chip ( TL2 << TL1) . Please double check the
HDMI Rx chip datasheet for this design requirement.
TL3 routing should follow the datasheet of the HDMI RX chip.
All routing use 4x8 or 4x10 mil nominal trace impedance 55 +/- 10%.
All signals should be referenced to ground. Reference to unbroken power plane is also
accepted.
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