Samsung RT55EANS Especificações Página 102

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102 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
Figure 8-14. GBE_RXDATA<0~3> and GBE_RXCLK
Table 8-7. GBE RX Routing Guidelines
Traces Description Layer
Min
Length
Max
Length
Trace
Width
Spacing Notes
TL1 SDV Breakout
Micro
strip
0.1” 0.5” 4 Mils >=4 Mils
TL2 Lead-in 1
Micro
strip 0.5” 6.5” 4 Mils >=10 Mils
TL3 GBE Breakout
Micro
strip 0.1” 0.5” 4 Mils >=4 Mils
Length
match
±0.25” TL1+TL2+TL3
Notes:
GBE RX signal group: GBE_RXCLK, GBE_RXCTL, and GBE_RXDATA<0-3>. Match all signals with in +/-
0.25”respect to its clock.
All trace impedance required to be 55 Ω +/- 10%.
Trace widths provided here are targeted only for 55 Ω.
All signals should be referenced to ground. Reference to unbroken power plane is also accepted.
No additional probe points to be used. Minimize the vias to be used.
This guides is based on RTL8211 PHY used on Intel development board. For PHY devices other than
RTL8211, refer to the Vendor’s routing guideline.
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