Samsung S3F84A5 Manual do Utilizador

Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2009 Samsung Electronics, Inc. All Rights Reserved USER'S MANUAL S3F84A5

x S3F84A5_UM_REV1.10 MICROCONTROLLER Table of Contents (Continued) Chapter 4 Control Registers Overview...

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-20 P1INT — Port 1 Interrupt Control Register E7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-21 P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 0 Bit Identifier

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-22 P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-23 P3CONH — Port 3 Control Register (High Byte) ECH Set 1, Bank 0 Bit Identifier

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-24 P3CONL — Port 3 Control Register (Low Byte) EDH Set 1, Bank 0 Bit Identifier

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-25 P3INT — Port 3 Interrupt Control Register EEH Set 1, Bank 0 Bit Ide

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-26 P3PND — Port 3 Interrupt Pending Register EFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-27 P3PUR — Port 3 Pull-up Resistor Control Register F0H Set1, Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-28 PP — Register Page Pointer DFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-29 PWMCON — PWM Control Register F1H Set 1, Bank 0 Bit Identifie

S3F84A5_UM_REV1.10 MICROCONTROLLER xi Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview...

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-30 P2PWMOUT— Port 2 PWM Output Control Register F2H Set 1, Bank 0 Bit Identifier .7 .6 .5

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-31 PWMINT— PWM Interrupt Control Register F4H Set 1, Bank 0 Bit Identifier

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-32 RESETID— Reset Source Indicating Register F3H Set 1, Bank1 Bit Identifier

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-33 RP0 — Register Pointer 0 D6H Set 1, Ban

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-34 SPH — Stack Pointer (High Byte) D8H Set 1, Bank0

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-35 STPCON — Stop Control Register D1H Set 1, Bank0 Bi

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-36 SYM — System Mode Register DEH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-37 T0CON — Timer 0 Control Register E8H Set 1, Bank 1 Bit Id

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-38 TACON — Timer A Control Register E4H Set 1, Bank 1 Bit I

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-39 TBCON — Timer B Control Register E5H Set 1, Bank 1 Bit Iden

xii S3F84A5_UM_REV1.10 MICROCONTROLLER Table of Contents (Continued) Chapter 11 8-Bit Timer A/B 8-Bit Timer A...

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-40 TINTPND — Timer Interrupt Pending Register F1H Set 1, Bank 1 Bit Identifie

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-41 UARTCON — UART Control Register F5H Set 1, Bank 0 Bit Identifie

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-42 UARTPND — UART Interrupt Pending Register F6H Set 1, Bank 0 Bit Identifier .

S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE 5-1 5 INTERRUPT STRUCTURE OVERVIEW The S3F8-series interrupt structure has three basic components: levels,

INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 5-2 INTERRUPT TYPES The three components of the S3F8 interrupt structure described before — levels, vecto

S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE 5-3 S3F84A5 INTERRUPT STRUCTURE The S3F84A5 microcontroller supports 17 interrupt sources. Every interrupt

INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 5-4 Vectors SourcesLevels Reset/ClearD0H Timer A overflowIRQ0D2H Timer A match/captureH/W,S/WS/WNOTES:1.

S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE 5-5 Interrupt Vector Addresses All interrupt vector addresses for the S3F84A5 interrupt structure is stored

INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 5-6 Enable/Disable Interrupt Instructions (EI, DI) Executing the Enable Interrupts (EI) instruction globa

S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE 5-7 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globa

S3F84A5_UM_REV1.10 MICROCONTROLLER xiii Table of Contents (Continued) Chapter 15 10-bit A/D Converter Overview...

INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 5-8 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding p

S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE 5-9 SYSTEM MODE REGISTER (SYM) The system mode register, SYM (DEH, Set1), is used to globally enable and di

INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 5-10 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set1) is used to enable or disa

S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE 5-11 INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set1, Bank0), is used to

INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 5-12 Interrupt Priority Register (IPR)FFH, Set1, Bank0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBGroup A0 = IRQ0

S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE 5-13 INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (DCH,

INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 5-14 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type th

S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE 5-15 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows:

INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 5-16 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the ad

S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE 5-17 FAST INTERRUPT PROCESSING (Continued) Two other system registers support fast interrupt processing: —

xiv S3F84A5_UM_REV1.10 MICROCONTROLLER Table of Contents (Continued) Chapter 19 Mechanical Data Overview...

INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 5-18 NOTES

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-1 6 INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files t

INSTRUCTION SET S3F84A5_UM_REV1.10 6-2 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-3 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions A

INSTRUCTION SET S3F84A5_UM_REV1.10 6-4 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instruct

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-5 Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instruct

INSTRUCTION SET S3F84A5_UM_REV1.10 6-6 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits which describe the current status of

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithme

INSTRUCTION SET S3F84A5_UM_REV1.10 6-8 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-9 Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code

S3F84A5_UM_REV1.10 MICROCONTROLLER xv List of Figures Figure Title Page Number Number 1-1 S3F84A5 Block Diagram ...

INSTRUCTION SET S3F84A5_UM_REV1.10 6-10 Table 6-5. OPCODE Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 A

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-11 Table 6-5. OPCODE Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r

INSTRUCTION SET S3F84A5_UM_REV1.10 6-12 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-13 INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each ins

INSTRUCTION SET S3F84A5_UM_REV1.10 6-14 ADC — Add with Carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the ca

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-15 ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination ope

INSTRUCTION SET S3F84A5_UM_REV1.10 6-16 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-17 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ←

INSTRUCTION SET S3F84A5_UM_REV1.10 6-18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-19 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the speci

xvi S3F84A5_UM_REV1.10 MICROCONTROLLER List of Figures (Continued) Figure Title Page Number Number 3-1 Register Addressing...

INSTRUCTION SET S3F84A5_UM_REV1.10 6-20 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit withi

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within th

INSTRUCTION SET S3F84A5_UM_REV1.10 6-22 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← d

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then

INSTRUCTION SET S3F84A5_UM_REV1.10 6-24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b)

INSTRUCTION SET S3F84A5_UM_REV1.10 6-26 CALL — Call Procedure CALL dst Operation: SP ← SP–1 @SP ← PCL SP ← SP–1 @SP ← PCH PC ← ds

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-27 CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = &quo

INSTRUCTION SET S3F84A5_UM_REV1.10 6-28 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0&quo

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-29 COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are comple

S3F84A5_UM_REV1.10 MICROCONTROLLER xvii List of Figures (Continued) Figure Title Page Number Number 9-1 Port 0 Control Register (P0CON)...

INSTRUCTION SET S3F84A5_UM_REV1.10 6-30 CP — Compare CP dst,src Operation: dst–src The source operand is compared to (subtracted from) the dest

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-31 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst–src = "0",

INSTRUCTION SET S3F84A5_UM_REV1.10 6-32 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst–src ≠ "0&

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-33 DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4-

INSTRUCTION SET S3F84A5_UM_REV1.10 6-34 DA — Decimal Adjust DA (Continued) Example: Given: The working register R0 contains the value 15 (BCD)

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-35 DEC — Decrement DEC dst Operation: dst ← dst–1 The contents of the destination operand are decremente

INSTRUCTION SET S3F84A5_UM_REV1.10 6-36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (wh

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0,

INSTRUCTION SET S3F84A5_UM_REV1.10 6-38 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-39 DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC

xviii S3F84A5_UM_REV1.10 MICROCONTROLLER List of Figures (Concluded) Figure Title Page Number Number 14-1 UART Control Register (UARTCON)...

INSTRUCTION SET S3F84A5_UM_REV1.10 6-40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 The EI instruction sets bit zero of the system mod

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This

INSTRUCTION SET S3F84A5_UM_REV1.10 6-42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instructio

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-43 IDLE — Idle Operation IDLE Operation: (See description) The IDLE instruction stops the CPU clock while

INSTRUCTION SET S3F84A5_UM_REV1.10 6-44 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are in

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-45 INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which

INSTRUCTION SET S3F84A5_UM_REV1.10 6-46 IRET — Interrupt Return IRET IRET (Normal) RET (Fast) Operation: FLAGS ← @SP PC ↔ IP SP ← S

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-47 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst

INSTRUCTION SET S3F84A5_UM_REV1.10 6-48 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition specified

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-49 LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination.

S3F84A5_UM_REV1.10 MICROCONTROLLER xix List of Figures (Concluded) Figure Title Page Number Number 18-1 Input Timing for External Interrupts...

INSTRUCTION SET S3F84A5_UM_REV1.10 6-50 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-51 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The s

INSTRUCTION SET S3F84A5_UM_REV1.10 6-52 LDC/LDE — Load Memory LDC dst,src LDE dst,src Operation: dst ← src This instruction loads a byte fro

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-53 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 0

INSTRUCTION SET S3F84A5_UM_REV1.10 6-54 LDCD/LDED — Load Memory and Decrement LDCD dst,src LDED dst,src Operation: dst ← src rr ← rr

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-55 LDCI/LDEI — Load Memory and Increment LDCI dst,src LDEI dst,src Operation: dst ← src rr ← rr +

INSTRUCTION SET S3F84A5_UM_REV1.10 6-56 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD dst,src LDEPD dst,src Operation: rr ← rr – 1

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-57 LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI dst,src LDEPI dst,src Operation: rr ← rr + 1

INSTRUCTION SET S3F84A5_UM_REV1.10 6-58 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded in

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-59 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand

Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication

INSTRUCTION SET S3F84A5_UM_REV1.10 6-60 NEXT — Next NEXT Operation: PC ← @IP IP ← IP + 2 The NEXT instruction is useful when implementing

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-61 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typical

INSTRUCTION SET S3F84A5_UM_REV1.10 6-62 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-63 POP — Pop from Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addre

INSTRUCTION SET S3F84A5_UM_REV1.10 6-64 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instru

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-65 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI in

INSTRUCTION SET S3F84A5_UM_REV1.10 6-66 PUSH — Push to Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements t

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-67 PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instruc

INSTRUCTION SET S3F84A5_UM_REV1.10 6-68 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This ins

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-69 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless

S3F84A5_UM_REV1.10 MICROCONTROLLER xxi List of Tables Table Title Page Number Number 1-1 Pin Descriptions of 28-SOP, 28-SSOP (32-ELP)...

INSTRUCTION SET S3F84A5_UM_REV1.10 6-70 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return t

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-71 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n

INSTRUCTION SET S3F84A5_UM_REV1.10 6-72 RLC — Rotate Left through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← d

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-73 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n) ← dst (n + 1), n

INSTRUCTION SET S3F84A5_UM_REV1.10 6-74 RRC — Rotate Right through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-75 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLA

INSTRUCTION SET S3F84A5_UM_REV1.10 6-76 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAG

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-77 SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along

INSTRUCTION SET S3F84A5_UM_REV1.10 6-78 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of i

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-79 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (

xxii S3F84A5_UM_REV1.10 MICROCONTROLLER List of Tables Table Title Page Number Number 20-1 Descriptions of Pins Used to Read/Write the Flash ROM..

INSTRUCTION SET S3F84A5_UM_REV1.10 6-80 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-81 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock

INSTRUCTION SET S3F84A5_UM_REV1.10 6-82 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the d

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-83 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four

INSTRUCTION SET S3F84A5_UM_REV1.10 6-84 TCM — Test Complement under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests s

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-85 TM — Test under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the

INSTRUCTION SET S3F84A5_UM_REV1.10 6-86 WFI — Wate for Interrupt WFI Operation: The CPU is effectively halted before an interrupt occurs, excep

S3F84A5_UM_REV1.10 INSTRUCTION SET 6-87 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logicall

INSTRUCTION SET S3F84A5_UM_REV1.10 6-88 NOTES

S3F84A5_UM_REV1.10 CLOCK CIRCUIT 7-1 7 CLOCK CIRCUIT OVERVIEW By smart option (3FH.2 – .1 in ROM), user can select internal RC oscillator, or

S3F84A5_UM_REV1.10 MICROCONTROLLER xxiii List of Programming Tips Description Page Number Chapter 2: Address Spaces Using the Page Pointer for

CLOCK CIRCUIT S3F84A5_UM_REV1.10 7-2 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect clock oscill

S3F84A5_UM_REV1.10 CLOCK CIRCUIT 7-3 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in location D

CLOCK CIRCUIT S3F84A5_UM_REV1.10 7-4 STOP Control Register (STPCON)D1H, Set 1, R/W.7 .6 .5 .4 .3 .2 .1 .0 LSBSTOP Control bits:Other values = Di

S3F84A5_UM_REV1.10 RESET and POWER-DOWN 8-1 8 RESET and POWER-DOWN SYSTEM RESET OVERVIEW By smart option (3FH.6 and 3FH.0 in ROM), user can select

RESET and POWER-DOWN S3F84A5_UM_REV1.10 8-2 +-VREFCMOS REF VDDVREFVIN VDDN.FnRESETWhen the VDD levelis lower than VLVR ComparatorNOTES:1. The

S3F84A5_UM_REV1.10 RESET and POWER-DOWN 8-3 MCU Initialization Sequence The following sequence of events occurs during a Reset operation: — All i

RESET and POWER-DOWN S3F84A5_UM_REV1.10 8-4 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode,

S3F84A5_UM_REV1.10 RESET and POWER-DOWN 8-5 Sources to Release Stop Mode Stop mode is released when following sources go active: — System Reset b

RESET and POWER-DOWN S3F84A5_UM_REV1.10 8-6 HARDWARE RESET VALUES The reset values for CPU and system registers, peripheral control registers, a

S3F84A5_UM_REV1.10 RESET and POWER-DOWN 8-7 Table 8-2. S3F84A5 Set1 Bank0 Registers Values after RESET Register Name Mnemonic Address R/W RESET

RESET and POWER-DOWN S3F84A5_UM_REV1.10 8-8 Table 8-3. S3F84A5 Set1 Bank1 Registers Values after RESET Register Name Mnemonic Address R/W RES

S3F84A5_UM_REV1.10 I/O PORTS 9-1 9 I/O PORTS OVERVIEW The S3F84A5 microcontroller has four bit-programmable I/O ports, P0-P3. The port 0 and 3 a

I/O PORTS S3F84A5_UM_REV1.10 9-2 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all four S3F84A5 I/O port data

S3F84A5_UM_REV1.10 I/O PORTS 9-3 PORT 0 Port 0 is an 3-bit I/O port that you can use two ways: — General-purpose digital I/O — Alternative fun

I/O PORTS S3F84A5_UM_REV1.10 9-4 Port 0 Control Register (P0CON)E6H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5.4.3.2.1.0.5 .4 bit/P0.2000110

S3F84A5_UM_REV1.10 I/O PORTS 9-5 PORT 1 Port 1 is a 8-bit I/O port with individually configurable pins that you can use two ways: — General-purp

I/O PORTS S3F84A5_UM_REV1.10 9-6 Port 1 Control Register, High Byte (P1CONH)E8H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5.4.3 .2.1.0.7 .6

S3F84A5_UM_REV1.10 I/O PORTS 9-7 Port 1 Control Register, Low Byte (P1CONL)E9H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5 .4.3.2 .1.0.7 .6 bi

I/O PORTS S3F84A5_UM_REV1.10 9-8 Port 1 Interrupt Control Register (P1INT)E7H, Set1, Bank0, R/W, Reset value:00HLSBMSB .7 .6 .5 .4 .3 .2 .1 .0N

S3F84A5_UM_REV1.10 I/O PORTS 9-9 PORT 2 Port 2 is an 8-bit I/O port that you can use two ways: — General-purpose I/O — Alternative function Port

S3F84A5_UM_REV1.10 MICROCONTROLLER xxv List of Register Descriptions Register Full Register Name Page Identifier Number ADCONH A/D Converter Con

I/O PORTS S3F84A5_UM_REV1.10 9-10 Port 2 Control Register, High Byte (P2CONH)EAH, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6 .5.4.3.2.1.0.7 .6

S3F84A5_UM_REV1.10 I/O PORTS 9-11 Port 2 Control Register, Low Byte (P2CONL)EBH, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5 .4.3.2.1.0.7 .6 b

I/O PORTS S3F84A5_UM_REV1.10 9-12 PORT 3 Port 3 is a 5-bit I/O Port that you can use two ways: — General-purpose I/O — Alternative function Port

S3F84A5_UM_REV1.10 I/O PORTS 9-13 Port 3 Pull-up Resistor Control Registers (P3PUR) Using the port 3 pull-up control register, P3PUR(F0H, Set 1,

I/O PORTS S3F84A5_UM_REV1.10 9-14 Port 3 Control Register, Low Byte (P3CONL)EDH, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5.4.3.2.1.0.7 .6 bi

S3F84A5_UM_REV1.10 I/O PORTS 9-15 Port 3 Interrupt Control Register (P3INT)EEH, Set1, Bank0, R/W, Reset value: 00H.7 .6 .5 .4 .3 .2 .1 .0MSB LSBP

I/O PORTS S3F84A5_UM_REV1.10 9-16 Port 3 Pull-up Resistor Control Register (P3PUR)F0H, Set1, Bank0, R/W, Reset value: 00H.7 .6 .5 .4 .3 .2 .1 .

S3F84A5_UM_REV1.10 I/O PORTS 9-17  PROGRAMMING TIP — Using Ports ORG 0000H ;--------------<< Smart Option >> ORG 003CH DB 0FFH

I/O PORTS S3F84A5_UM_REV1.10 9-18 NOTES

S3F84A5_UM_REV1.10 BASIC TIMER 10-1 10 BASIC TIMER OVERVIEW Basic Timer (BT) You can use the basic timer (BT) in two different ways: — As a wat

BASIC TIMER S3F84A5_UM_REV1.10 10-2 BASIC TIMER (BT) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to sel

S3F84A5_UM_REV1.10 BASIC TIMER 10-3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOV

BASIC TIMER S3F84A5_UM_REV1.10 10-4 Oscillation Stabilization TimeNormal Operating mode0.8 VDDtWAIT = (4096x16)/fOSCBasic timer increment andCPU

S3F84A5_UM_REV1.10 BASIC TIMER 10-5 NOTE: Duration of the oscillator stabilzation wait time, tWAIT, it is released by aninterrupt is determined by

BASIC TIMER S3F84A5_UM_REV1.10 10-6  PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to sample

S3F84A5_UM_REV1.10 8-BIT TIMER A/B 11-1 11 8-BIT TIMER A/B 8-BIT TIMER A OVERVIEW The 8-bit timer A is an 8-bit general-purpose timer/counter.

8-BIT TIMER A/B S3F84A5_UM_REV1.10 11-2 FUNCTION DESCRIPTION Timer A Interrupts The timer A module can generate two interrupts: the timer A ove

S3F84A5_UM_REV1.10 8-BIT TIMER A/B 11-3 TIMER A CONTROL REGISTER (TACON) You use the timer A control register, TACON — Select the timer A oper

8-BIT TIMER A/B S3F84A5_UM_REV1.10 11-4 Timer Interrupt Pending Register (TINTPND)F1H, Set1, Bank1, Reset: 00H, R/WLSBMSB .7 .6 .5 .4 .3 .2 .1 .

S3F84A5_UM_REV1.10 8-BIT TIMER A/B 11-5 BLOCK DIAGRAM Figure 11-4. Simplified Timer A Functional Block Diagram

S3F84A5_UM_REV1.10 MICROCONTROLLER xxvii List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add with Carr

8-BIT TIMER A/B S3F84A5_UM_REV1.10 11-6 8-BIT TIMER B OVERVIEW The 8-bit timer B is an 8-bit general-purpose timer/counter. Timer B has two oper

S3F84A5_UM_REV1.10 8-BIT TIMER A/B 11-7 FUNCTION DESCRIPTION Timer B Interrupts The timer B module can generate two interrupts: the timer B ove

8-BIT TIMER A/B S3F84A5_UM_REV1.10 11-8 Table 11-1. Timer B PWM output "stretch" Values for Extension Data Register (TBDATAEX .1−.0) T

S3F84A5_UM_REV1.10 8-BIT TIMER A/B 11-9 1st 2nd 3rd 4th 1st 2nd 3rd 4th500 ns750 ns0H 100H4 MHz0H 100HTimer B Clock: 4 MHz00000010Bxxxxxx01BTBDA

8-BIT TIMER A/B S3F84A5_UM_REV1.10 11-10 TIMER B CONTROL REGISTER (TBCON) The control register for the Timer B, TBCON, is located at register ad

S3F84A5_UM_REV1.10 8-BIT TIMER A/B 11-11 Timer B Data Register (TBDATA)E7H, Set1, Bank1, R/WLSBMSB.7.6 .5.4 .3 .2.1.0Reset Value: FFh Figure 11-

8-BIT TIMER A/B S3F84A5_UM_REV1.10 11-12 BLOCK DIAGRAM NOTES:1. When Timer B operate at “8+2”bit PWM mode, match signal cannot clear cou

S3F84A5_UM_REV1.10 8-BIT TIMER A/B 11-13 ) PROGRAMMING TIP — Using the Timer A ;--------------<< Interrupt Vector Address >> ORG

8-BIT TIMER A/B S3F84A5_UM_REV1.10 11-14 ) PROGRAMMING TIP — Programming the Timer B "8+2" Bit PWM Mode ;--------------<< Inte

S3F84A5_UM_REV1.10 16-BIT TIMER 0 12-1 12 16-BIT TIMER 0 OVERVIEW The S3F84A5 has one 16-bit timer/counter. The 16-bit timer 0 is a 16-bit g

xxviii S3F84A5_UM_REV1.10 MICROCONTROLLER List of Instruction Descriptions (Continued) Instruction Full Register Name Page Mnemonic Number LDC/LDE

16-BIT TIMER 0 S3F84A5_UM_REV1.10 12-2 FUNCTION DESCRIPTION Timer 0 Interrupts The timer 0 module can generate two interrupts, the timer 0 over

S3F84A5_UM_REV1.10 16-BIT TIMER 0 12-3 TIMER 0 CONTROL REGISTER (T0CON) You use the Timer 0 control register, T0CON, to — Select the Timer 0

16-BIT TIMER 0 S3F84A5_UM_REV1.10 12-4 Timer Interrupt Pending Register (TINTPND)F1H, Set1, Bank1, Reset: 00H, R/WLSBMSB .7 .6 .5 .4 .3 .2 .1 .0

S3F84A5_UM_REV1.10 16-BIT TIMER 0 12-5 BLOCK DIAGRAM fxx/1fxx/64fxx/8VSST0CKfxx/256fxx/1024NOTES:1. When PWM mode, match signal cannot clear

16-BIT TIMER 0 S3F84A5_UM_REV1.10 12-6 ) PROGRAMMING TIP — Using the Timer 0 ORG 0000h VECTOR 0E4h, INT_Timer0_match ORG 0100h INITIAL: DI

S3F84A5_UM_REV1.10 8-BIT PWM (PULSE WIDTH MODULATION) 13-1 13 8-BIT PWM (PULSE WIDTH MODULATION) OVERVIEW This microcontroller’s PWM module has on

8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 13-2 PWM Counter The PWM 8-bit counter is a bi-directional counter. Depending on the PWM mod

S3F84A5_UM_REV1.10 8-BIT PWM (PULSE WIDTH MODULATION) 13-3 PWM Mode The PWM module has two operation modes. Edge aligned PWM mode and center aligne

8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 13-4 Center Aligned PWM Mode In center aligned PWM mode, counter counts from 00H to FFH and

S3F84A5_UM_REV1.10 8-BIT PWM (PULSE WIDTH MODULATION) 13-5 Programmable Dead-time generation In motor control applications, the power output device

S3F84A5_UM_REV1.10 PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW S3F8-SERIES MICROCONTROLLERS Samsung's SAM8RC family of 8-bit single-chip CMOS

8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 13-6 Table 13-1. PWM selectable waveform mode and group compare output mode for PWM Control

S3F84A5_UM_REV1.10 8-BIT PWM (PULSE WIDTH MODULATION) 13-7 PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is locate

8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 13-8 PORT2 PWM OUTPUT CONTROL REGISTER (P2PWMOUT) The port 2 PWM output control register for

S3F84A5_UM_REV1.10 8-BIT PWM (PULSE WIDTH MODULATION) 13-9 PWM INTERRUPT CONTROL REGISTER (PWMINT) The PWM interrupt control register, PWMINT, is l

8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 13-10 PWM COMPARE DATA REGISTER (PWMADATA & PWMBDATA) There are two compare data registe

S3F84A5_UM_REV1.10 8-BIT PWM (PULSE WIDTH MODULATION) 13-11 BLOCK DIAGRAM MUXfxx/256fxx/64fxx/8fxxPWMCON.7-.6PWMCON.08-bit CounterDirectionPWMCON.

8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 13-12 ) PROGRAMMING TIP — Programming the PWM Module to output 6 channels Edge Aligned PWM

S3F84A5_UM_REV1.10 8-BIT PWM (PULSE WIDTH MODULATION) 13-13 INT_PWMAMATCH: ; PWM A group compare match interrupt service routine • AND PWMIN

8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 13-14 ) PROGRAMMING TIP — Programming the PWM Module to 3 complementary outputs in Center A

S3F84A5_UM_REV1.10 8-BIT PWM (PULSE WIDTH MODULATION) 13-15 JR t,MAIN ;--------------<< Subroutines >> SR_PWMDUTY: ; PWM d

S3F84A5_UM_REV1.10 MICROCONTROLLER iii Preface The S3F84A5 Microcontroller User's Manual is designed for application designers and programmers

PRODUCT OVERVIEW S3F84A5_UM_REV1.10 1-2 FEATURES CPU • SAM8RC CPU core Memory • 400-byte general-purpose register (RAM) • 16K-byte internal m

8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 13-16 NOTES

S3F84A5_UM_REV1.10 UART 14-1 14 UART OVERVIEW The UART block has a full-duplex serial port with programmable operating modes: There is one sync

UART S3F84A5_UM_REV1.10 14-2 UART CONTROL REGISTER (UARTCON) The control register for the UART is called UARTCON at address F5H, Set1 Bank0. It

S3F84A5_UM_REV1.10 UART 14-3 UART INTERRUPT PENDING REGISTER (UARTPND) The UART interrupt pending register, UARTPND is located at address F6H,

UART S3F84A5_UM_REV1.10 14-4 UART DATA REGISTER (UDATA) UART Data Register (UDATA) F8H, Set1, Bank0, R/W, Reset Value: FFHMSB LSB.5.4.1.0.7 .6

S3F84A5_UM_REV1.10 UART 14-5 BAUD RATE CALCULATIONS The baud rate is determined by the baud rate data register, 8bit BRDATA Mode 0 baud rate

UART S3F84A5_UM_REV1.10 14-6 BLOCK DIAGRAM Zero DetectorUDATARxD (P0.0)TIERIEInterrupt1-to-0 Transition DetectorRERIEBit DetectorShiftValueMS0M

S3F84A5_UM_REV1.10 UART 14-7 UART MODE 0 FUNCTION DESCRIPTION In mode 0, UART is input and output through the RxD (P0.0) pin and TxD (P0.1) pin

UART S3F84A5_UM_REV1.10 14-8 UART MODE 1 FUNCTION DESCRIPTION In mode 1, 10-bits are transmitted (through the TxD (P0.1) pin) or received (thro

S3F84A5_UM_REV1.10 UART 14-9 UART MODE 2 FUNCTION DESCRIPTION In mode 2, 11-bit are transmitted through the TxD pin or received through the RxD

S3F84A5_UM_REV1.10 PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM I/O Port and Interrupt ControlSAM8RC CPU16-KbyteROM400-ByteRAMOSC/nRESET8-BitBasic Timer8-B

UART S3F84A5_UM_REV1.10 14-10 UART MODE 3 FUNCTION DESCRIPTION In mode 3, 11-bits are transmitted (through the TxD) or received (through the Rx

S3F84A5_UM_REV1.10 UART 14-11 SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3F8-series multiprocessor communication features let

UART S3F84A5_UM_REV1.10 14-12 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications:

S3F84A5_UM_REV1.10 10-BIT A/D CONVERTER 15-1 15 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successiv

10-BIT A/D CONVERTER S3F84A5_UM_REV1.10 15-2 The A/D converter then enters an idle state. If you are not using event trigger, you should reset

S3F84A5_UM_REV1.10 10-BIT A/D CONVERTER 15-3 A/D CONVERTER HIGH BYTE CONTROL REGISTER (ADCONH) The A/D converter high-byte control register, ADC

10-BIT A/D CONVERTER S3F84A5_UM_REV1.10 15-4 A/D Converter High-byte Control Register (ADCONH)FBH, Set1, Bank0, Reset=00H, R/WLSBMSB.7.6 .5 .4.

S3F84A5_UM_REV1.10 10-BIT A/D CONVERTER 15-5 Conversion Data Register High Byte (ADDATAH)F9H, Set1, Bank0, Read onlyLSBMSB.7.6.5.4.3.2.1.0Conver

10-BIT A/D CONVERTER S3F84A5_UM_REV1.10 15-6 BLOCK DIAGRAM D/A ConverterAVrefVSS- A/D Converter High Byte Control Register ADCONH (FBH)ADCONH.6

S3F84A5_UM_REV1.10 10-BIT A/D CONVERTER 15-7 INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of VSS and

PRODUCT OVERVIEW S3F84A5_UM_REV1.10 1-4 PIN ASSIGNMENT VSS(Vpp)TESTRxD/P0.0TxD/P0.1nRESET/P0.2AVREFINT0/ADC0/P1.0INT1/ADC1/P1.1ADC2/P1.2ADC3/P1.

10-BIT A/D CONVERTER S3F84A5_UM_REV1.10 15-8  PROGRAMMING TIP — Configuring A/D Converter (1) End of ADC conversion complete: check EOC flag

S3F84A5_UM_REV1.10 10-BIT A/D CONVERTER 15-9  PROGRAMMING TIP — Configuring A/D Converter (2) End of ADC conversion complete: A/D converter co

10-BIT A/D CONVERTER S3F84A5_UM_REV1.10 15-10 NOTES

S3F84A5_UM_REV1.10 LOW VOLTAGE RESET 16-1 16 LOW VOLTAGE RESET OVERVIEW By smart option (3FH.6 in ROM), user can select internal RESET (LVR) or

LOW VOLTAGE RESET S3F84A5_UM_REV1.10 16-2 +-VREFCMOS REF VDDVREFVIN VDDN.FnRESETWhen the VDD levelis lower than VLVR ComparatorNOTES:1. The ta

S3F84A5_UM_REV1.10 Embedded Flash Memory Interface 17-1 17 EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F84A5 has an on-chip flash memory inte

Embedded Flash Memory Interface S3F84A5_UM_REV1.10 17-2 ISPTM (ON-BOARD PROGRAMMING) SECTOR ISPTM sectors located in program memory area can sto

S3F84A5_UM_REV1.10 Embedded Flash Memory Interface 17-3 Figure 17-2. Smart Option

Embedded Flash Memory Interface S3F84A5_UM_REV1.10 17-4 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have

S3F84A5_UM_REV1.10 Embedded Flash Memory Interface 17-5 FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) FLASH MEMORY CONTROL REGISTER (FMCON)

S3F84A5_UM_REV1.10 PRODUCT OVERVIEW 1-5 S3F84A5(Top View)32-ELP(Vpp)TESTRxD/P0.012345678(SDAT)INT3/P3.1(SCLK)INT4/P3.2VDDVSSXout/P3.3Xin/P3.4P1.1

Embedded Flash Memory Interface S3F84A5_UM_REV1.10 17-6 FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for the er

S3F84A5_UM_REV1.10 Embedded Flash Memory Interface 17-7 SECTOR ERASE User can erase a flash memory partially by using sector erase function only

Embedded Flash Memory Interface S3F84A5_UM_REV1.10 17-8 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming En

S3F84A5_UM_REV1.10 Embedded Flash Memory Interface 17-9  PROGRAMMING TIP — Sector Erase Case1. Erase one sector • • ERASE_ONESECTOR:

Embedded Flash Memory Interface S3F84A5_UM_REV1.10 17-10 SECTOR_ERASE: LD R12,SecNumH LD R14,SecNumL

S3F84A5_UM_REV1.10 Embedded Flash Memory Interface 17-11 PROGRAMMING A flash memory is programmed in one-byte unit after sector erase. The writ

Embedded Flash Memory Interface S3F84A5_UM_REV1.10 17-12 SB1Start; Select Bank1; User Program Mode Enable; Set Secotr Base Address; Write data

S3F84A5_UM_REV1.10 Embedded Flash Memory Interface 17-13 SB1Start; Select Bank1; User Program Mode Enable; Set Secotr Base Address; Write data

Embedded Flash Memory Interface S3F84A5_UM_REV1.10 17-14  PROGRAMMING TIP — Programming Case1. 1-Byte Programming • • WR_BYTE:

S3F84A5_UM_REV1.10 Embedded Flash Memory Interface 17-15 Case3. Programming to the flash memory space located in other sectors • • WR_INSECTOR2

PRODUCT OVERVIEW S3F84A5_UM_REV1.10 1-6 PIN DESCRIPTIONS Table 1-1. Pin Descriptions of 28-SOP, 28-SSOP (32-ELP) Pin Names Pin Type Pin Descript

Embedded Flash Memory Interface S3F84A5_UM_REV1.10 17-16 READING The read operation starts by ‘LDC’ instruction. The program procedure in user

S3F84A5_UM_REV1.10 Embedded Flash Memory Interface 17-17 HARD LOCK PROTECTION User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4.

Embedded Flash Memory Interface S3F84A5_UM_REV1.10 17-18 NOTES

S3F84A5_UM_REV1.10 ELECTRICAL DATA 18-1 18 ELECTRICAL DATA OVERVIEW In this section, the following S3F84A5 electrical characteristics are present

ELECTRICAL DATA S3F84A5_UM_REV1.10 18-2 Table 18-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Unit Supply vol

S3F84A5_UM_REV1.10 ELECTRICAL DATA 18-3 Table 18-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Param

ELECTRICAL DATA S3F84A5_UM_REV1.10 18-4 Table 18-2. D.C. Electrical Characteristics (Continued) (TA = − 40 °C to + 85 °C, VDD = 2.0 V to

S3F84A5_UM_REV1.10 ELECTRICAL DATA 18-5 Table 18-3. A.C. Electrical Characteristics (TA = –40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Paramete

ELECTRICAL DATA S3F84A5_UM_REV1.10 18-6 10 MHzCPU Clock8 MHz1 MHz1234567Supply Voltage (V)2 MHz3 MHz4 MHz5.54.50.4 MHz Figure 18-3. Operating Vo

S3F84A5_UM_REV1.10 ELECTRICAL DATA 18-7 Table 18-4. Oscillator Characteristics (TA = – 40 °C to + 85 °C) Oscillator Clock Circuit Test Condi

S3F84A5_UM_REV1.10 PRODUCT OVERVIEW 1-7 Table 1-1. Pin Descriptions of 28-SOP, 28-SSOP (32-ELP) (Continued) Pin Names Pin Type Pin Description Ci

ELECTRICAL DATA S3F84A5_UM_REV1.10 18-8 Table 18-5. Oscillation Stabilization Time (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Oscil

S3F84A5_UM_REV1.10 ELECTRICAL DATA 18-9 Table 18-6. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.

ELECTRICAL DATA S3F84A5_UM_REV1.10 18-10 Execution ofSTOP Instruction~~VDDDR~~Stop ModeIdle ModeData Retention ModetWAITVDDInterruptNormal Opera

S3F84A5_UM_REV1.10 ELECTRICAL DATA 18-11 Table 18-8. UART Timing Characteristics in Mode 0 (10 MHz) (TA = – 40°C to + 85°C, 2.0 V to 5.5 V,

ELECTRICAL DATA S3F84A5_UM_REV1.10 18-12 Table 18-9. A/D Converter Electrical Characteristics (TA = − 40 °C to + 85 °C, VDD = 4.5 V to 5.5 V,

S3F84A5_UM_REV1.10 ELECTRICAL DATA 18-13 VEOBAVSS V2 V(K-1) V(K) VEOT AVREFAnalog InputDigital Output Figure 18-7. Definition of DLE and ILE Tabl

ELECTRICAL DATA S3F84A5_UM_REV1.10 18-14 Figure 18-8. The Circuit Diagram to Improve EFT Characteristics NOTE: To improve EFT characteristics,

S3F84A5_UM_REV1.10 MECHANICAL DATA 19-1 19 MECHANICAL DATA OVERVIEW The S3F84A5 is available in a 28-pin SOP package (28-SOP-375) , 28-pin SSO

MECHANICAL DATA S3F84A5_UM_REV1.10 19-2 28-SSOP-?#1 #14#15#28NOTE: Dimensions are in millimeters6.9? ± 0.25?5.25 ± 0.130.75 ± 0.190.18+ 0.07-

S3F84A5_UM_REV1.10 MECHANICAL DATA 19-3 Figure 19-3. 32-pin ELP Package Dimensions

PRODUCT OVERVIEW S3F84A5_UM_REV1.10 1-8 Table 1-2. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name

MECHANICAL DATA S3F84A5_UM_REV1.10 19-4 NOTES

S3F84A5_UM_REV1.10 S3F84A5 FLASH MCU 20-1 20 S3F84A5 FLASH MCU OVERVIEW The S3F84A5 single-chip CMOS microcontroller is the Flash MCU. It has an o

S3F84A5 FLASH MCU S3F84A5_UM_REV1.10 20-2 S3F84A5(Top View)32-ELP(Vpp)TESTRxD/P0.012345678(SDAT)INT3/P3.1(SCLK)INT4/P3.2VDDVSSXout/P3.3Xin/P3.4P1.

S3F84A5_UM_REV1.10 S3F84A5 FLASH MCU 20-3 Table 20-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name

S3F84A5 FLASH MCU S3F84A5_UM_REV1.10 20-4 ON BOARD WRITING The S3F84A5 needs only 6 signal lines including VDD and GND pins for writing internal f

S3F84A5_UM_REV1.10 S3F84A5 FLASH MCU 20-5 Reference Table for Connection Pin Name I/O mode in Applications Resistor (need) Required value Vpp(TE

S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS 21-1 21 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system on

DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 21-2 [Development System Configuration] Bus Figure 21-1. Development System Configuration

S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS 21-3 TB84A5 TARGET BOARD The TB84A5 target board is used for development of S3F84A5 microcontrollers. The TB8

DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 21-4 Table 21-1. Components of TB84A5 Symbols Usage Description J1 100-pin connector Connection between

S3F84A5_UM_REV1.10 PRODUCT OVERVIEW 1-9 PIN CIRCUITS IN Figure 1-4. Pin Circuit Type B (nRESET) P-ChannelN-ChannelVDDOutOutput DisableDataOpen-Dr

S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS 21-5 SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the tar

DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 21-6 Table 21-4. Using Single Header Pins to Select Clock Source and Operation mode Target Board Part Com

S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS 21-7 ONOFFLowHigh (Default)NOTES: 1. For EVA chip, smart option is determined by DIP switch not software. 2

DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 21-8 Table 21-6. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part

S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS 21-9 VSS(Top View)32-SDIP1133456910111213141516324302928272625232221201918XOUTS3C84T5RxD/P0.0J240-PIN DIP SOC

DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 21-10 THIRD PARTIES FOR DEVELOPMENT TOOLS SAMSUNG provides a complete line of development tools for SAMSUN

S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS 21-11 8-BIT IN-CIRCUIT EMULATOR AIJI System OPENice - i500 • TEL: 82-31-223-6611 • FAX: 82-331-223-6613 •

DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 21-12 OTP/MTP PROGRAMMER (WRITER) SPW-uni Single OTP/ MTP/FLASH Programmer • Download/Upload and data ed

S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS 21-13 OTP/MTP PROGRAMMER (WRITER) (Continued) GW-uni Gang Programmer for OTP/MTP/FLASH MCU • 8 devices prog

DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 21-14 NOTES

PRODUCT OVERVIEW S3F84A5_UM_REV1.10 1-10 I/OOutput DisablePAD DriverB Port Data INNoise FilterPull-upEnableVDDPort Data outputOpen-DrainExt.INT

S3F84A5_UM_REV1.10 PRODUCT OVERVIEW 1-11 I/OOutput DisablePAD DriverAPort Data outputAnalog Input Port Data INNoise FilterExt.INT Pull-upEnableVD

iv S3F84A5_UM_REV1.10 MICROCONTROLLER NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, SSCR PRODUCT NAME: S3F84A5 8-bit CMOS Microco

PRODUCT OVERVIEW S3F84A5_UM_REV1.10 1-12 I/OOutput DisablePAD DriverB Port Data INPull-upEnableVDDOpen-DrainAlternative InputDataPort Data outpu

S3F84A5_UM_REV1.10 PRODUCT OVERVIEW 1-13 I/OOutput DisablePAD DriverB Port Data INPull-upEnableVDDDataPort Data outputMUXAlternative outputMUXPWM

PRODUCT OVERVIEW S3F84A5_UM_REV1.10 1-14 I/OOutput DisablePAD DriverB Port Data INPull-upEnableVDDPort Data outputOpen-DrainAlternative Input Fi

S3F84A5_UM_REV1.10 PRODUCT OVERVIEW 1-15 I/OOutput DisablePAD DriverB Port Data INPull-upEnableVDDOpen-DrainnRESETMUXSmart optionPort Data output

PRODUCT OVERVIEW S3F84A5_UM_REV1.10 1-16 I/OOutput DisablePAD DriverA Port Data INPull-upEnableVDDPort Data outputAlternative Input Figure 1-17.

S3F84A5_UM_REV1.10 PRODUCT OVERVIEW 1-17 NOTES

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-1 2 ADDRESS SPACES OVERVIEW The S3F84A5 microcontroller has two kinds of address space: • Internal program

ADDRESS SPACES S3F84A5_UM_REV1.10 2-2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3F84A5 have 16Kbytes of

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-3 Smart Option Smart option is the ROM option for start condition of the chip. The ROM address used by smart

ADDRESS SPACES S3F84A5_UM_REV1.10 2-4 REGISTER ARCHITECTURE In the S3F84A5 implementation, the upper 64-byte area of register files is expanded t

S3F84A5_UM_REV1.10 MICROCONTROLLER v REVISION HISTORY Revision Date Remark 0.00 Dec, 2007 Preliminary Spec for internal release only. 0.09 July,

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-5 System Registers(Register Addressing Mode)General Purpose Register(Register Addressing Mode)Bank 1System a

ADDRESS SPACES S3F84A5_UM_REV1.10 2-6 REGISTER PAGE POINTER (PP) The S3F8-series architecture supports the logical expansion of the physical 256-

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-7  Programming Tip — Using the Page Pointer for RAM clear LD PP,#00H ; Destination ← 0, Source ← 0

ADDRESS SPACES S3F84A5_UM_REV1.10 2-8 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The up

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-9 PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3F84A5's a 256-byte register pages is call

ADDRESS SPACES S3F84A5_UM_REV1.10 2-10 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-11 USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are

ADDRESS SPACES S3F84A5_UM_REV1.10 2-12 16-byte Non-contiguous working register blockRegister File Contains 32 8-Byte Slices8-Byte Slice0H (R8)7H

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-13 REGISTER ADDRESSING The S3F8-series register architecture provides an efficient method of working registe

ADDRESS SPACES S3F84A5_UM_REV1.10 2-14 RP1RP0RegisterPointers00HAllAddressingModesPage 0,1Indirect Register,Indexed AddressingModesPage 0,1Regist

vi S3F84A5_UM_REV1.10 MICROCONTROLLER REVISION DESCRIPTIONS (REV 0.10) Chapter Chapter Name Page Subjects (Major changes comparing with last versio

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-15 COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select

ADDRESS SPACES S3F84A5_UM_REV1.10 2-16  PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-17 Together they create an8-bit register addressRegister pointerprovides fivehigh-order bitsAddress OPCODESe

ADDRESS SPACES S3F84A5_UM_REV1.10 2-18 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers i

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-19 8-bit addressform instruction'LD R11, R2'RP00 1 1 0 0 0 0 01 1 0 0 1 0 1 1Sele

ADDRESS SPACES S3F84A5_UM_REV1.10 2-20 SYSTEM AND USER STACK The S3F8-series microcontrollers use the system stack for data storage, subroutine c

S3F84A5_UM_REV1.10 ADDRESS SPACES 2-21  PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to p

S3F84A5_UM_REV1.10 ADDRESSING MODES 3-1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution us

ADDRESSING MODES S3F84A5_UM_REV1.10 3-2 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a spec

S3F84A5_UM_REV1.10 ADDRESSING MODES 3-3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the spec

S3F84A5_UM_REV1.10 MICROCONTROLLER vii REVISION DESCRIPTIONS (Rev 1.00) Chapter Chapter Name Page Subjects (Major changes comparing with last versi

ADDRESSING MODES S3F84A5_UM_REV1.10 3-4 INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODEPoints toRegister PairExampleInstructionReference

S3F84A5_UM_REV1.10 ADDRESSING MODES 3-5 INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODEADDRESS4-bitWorkingRegisterAddressPoint to theWork

ADDRESSING MODES S3F84A5_UM_REV1.10 3-6 INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODE4-bit WorkingRegister AddressSample Instructions:

S3F84A5_UM_REV1.10 ADDRESSING MODES 3-7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during ins

ADDRESSING MODES S3F84A5_UM_REV1.10 3-8 INDEXED ADDRESSING MODE (Continued) Register FileOPERANDProgram MemoryorData MemoryPoint to WorkingRegis

S3F84A5_UM_REV1.10 ADDRESSING MODES 3-9 INDEXED ADDRESSING MODE (Continued) Register FileOPERANDProgram MemoryorData MemoryPoint to WorkingRegist

ADDRESSING MODES S3F84A5_UM_REV1.10 3-10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bi

S3F84A5_UM_REV1.10 ADDRESSING MODES 3-11 DIRECT ADDRESS MODE (Continued) OPCODEProgram MemoryLower Address ByteMemoryAddressUsedUpper Address Byt

ADDRESSING MODES S3F84A5_UM_REV1.10 3-12 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located

S3F84A5_UM_REV1.10 ADDRESSING MODES 3-13 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between

viii S3F84A5_UM_REV1.10 MICROCONTROLLER REVISION DESCRIPTIONS (Rev 1.10) Chapter Chapter Name Page Subjects (Major changes comparing with last vers

ADDRESSING MODES S3F84A5_UM_REV1.10 3-14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-1 4 CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according t

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-2 Table 4-2. Set 1, Bank 0 Registers Register Name Mnemonic Address R/W RESETB Value (bit) Hex

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-3 Table 4-3. Set 1, Bank 1 Registers Register Name Mnemonic Address R/W RESETB Value (bit) Hex 7

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-4 FLAGS - System Flags Register.7 Carry Flag (C).6Zero Flag (Z).5Bit IdentifierRESET ValueRead/WriteR = R

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-5 ADCONH — A/D Converter Control Register (High Byte) FBH Set1, Bank0 Bit Identifier .7 .6 .5 .4 .3 .

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-6 ADCONL — A/D Converter Control Register (Low Byte) F3H Set1, Bank0 Bit Identifier .7 .6 .5 .4 .3 .2

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-7 BTCON — Basic Timer Control Register D3H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-8 CLKCON — System Clock Control Register D4H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Val

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-9 FLAGS — System Flags Register D5H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x

S3F84A5_UM_REV1.10 MICROCONTROLLER ix Table of Contents Part I — Programming Model Chapter 1 Product Overview S3F8-Series Microcontrollers...

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-10 FMCON — Flash Memory Control Register F4H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Rese

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-11 FMSECH — Flash Memory Sector Address Register (High Byte) F6H Set 1, Bank 1 Bit Identifier .7 .6 .5 .

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-12 FMUSR — Flash Memory User Programming Enable Register F5H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-13 IMR — Interrupt Mask Register DDH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value x x x x x

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-14 IPH — Instruction Pointer (High Byte) DAH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Valu

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-15 IPR — Interrupt Priority Register FFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Valu

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-16 IRQ — Interrupt Request Register DCH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-17 P0CON — Port 0 Control Register E6H Set 1, Bank 0 Bit

CONTROL REGISTERS S3F84A5_UM_REV1.10 4-18 P1CONH — Port 1 Control Register (High Byte) E8H Set 1, Bank 0 Bit Identifie

S3F84A5_UM_REV1.10 CONTROL REGISTER 4-19 P1CONL — Port 1 Control Register (Low Byte) E9H Set 1, Bank 0 Bit Identifier