Samsung S3F80P5X Manual do Utilizador

USER’S MANUAL S3F80P5X S3F80P5 MICROCONTROLLERS April 2010 REV 1.00 Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2009 Samsun

CONTROL REGISTERS S3F80P5_UM_ REV1.00 SPL — Stack Pointer (Low Byte) D9H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu

S3F80P5_UM_ REV1.00 CONTROL REGISTERS SYM — System Mode Register DEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 − − x

CONTROL REGISTERS S3F80P5_UM_ REV1.00 T0CON — Timer 0 Control Register D2H Set 1 Bank0 Bit Identifier .7 .6 .5 .4 .3

S3F80P5_UM_ REV1.00 CONTROL REGISTERS T1CON — Timer 1 Control Register FAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu

ADDRESSING MODES S3F80P5_UM_ REV1.00 T2CON − Timer 2 Control Register E8H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value

S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE 5 INTERRUPT STRUCTURE OVERVIEW The S3C8/S3F8-series interrupt structure has three basic components: levels

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT TYPES The three components of the S3C8/S3F8-series interrupt structure described above — levels,

S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE Vectors(14) Sources(17)Levels(7)IRQ0Timer 0 match/capture01Reset/ClearRESET100HBasic timer overflowFCHIRQ2

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F80P5 interrupt structure are stored in

S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE Table 5-1. S3F80P5 Interrupt Vectors Vector Address Interrupt Source Request Reset/ClearDecimal Value He

List of Figures Figure Title Page Number Number 1-1 Block Diagram (24-pin) ...

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) instruction globally en

S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding periphe

S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (DEH, Set 1, Bank0), is used to globally enable an

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set 1, and Bank0) is used to enable or

S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set 1, Bank 0), is used to set

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 Interrupt Priority Register(IPR)FEH, Set 1, Bank 0 , R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBGroup A0=IRQ0>IRQ

S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (DCH, Set 1

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: One type is automa

S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A

List of Figures (Continued) Figure Title Page Number Number 5-1 S3C8/S3F8-Series Interrupt Types ...

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (except smart option ROM Cell- 0

S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING (Continued) Two other system registers support fast interrupt processing: • The

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 NOTES 5-18

S3F80P5_UM_ REV1.00 INSTRUCTION SET 6 INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register fil

INSTRUCTION SET S3F80P5_UM_ REV1.00 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst, s

S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC d

INSTRUCTION SET S3F80P5_UM_ REV1.00 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions B

S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions

INSTRUCTION SET S3F80P5_UM_ REV1.00 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU ope

S3F80P5_UM_ REV1.00 INSTRUCTION SET FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic

List of Figures (Conclude) Figure Title Page Number Number 12-1 Counter A Block Diagram...

INSTRUCTION SET S3F80P5_UM_ REV1.00 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign

S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See

INSTRUCTION SET S3F80P5_UM_ REV1.00 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r

S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r1,R2 LD

INSTRUCTION SET S3F80P5_UM_ REV1.00 CONDITION CODES The op-code of a conditional jump always contains a 4-bit field called the condition code (cc).

S3F80P5_UM_ REV1.00 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instructi

INSTRUCTION SET S3F80P5_UM_ REV1.00 ADC — Add with Carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the s

S3F80P5_UM_ REV1.00 INSTRUCTION SET ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand

INSTRUCTION SET S3F80P5_UM_ REV1.00 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with

S3F80P5_UM_ REV1.00 INSTRUCTION SET BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b

INSTRUCTION SET S3F80P5_UM_ REV1.00 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to

S3F80P5_UM_ REV1.00 INSTRUCTION SET BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bi

INSTRUCTION SET S3F80P5_UM_ REV1.00 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit within the d

S3F80P5_UM_ REV1.00 INSTRUCTION SET BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the des

INSTRUCTION SET S3F80P5_UM_ REV1.00 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← dst(b) OR

S3F80P5_UM_ REV1.00 INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ←

INSTRUCTION SET S3F80P5_UM_ REV1.00 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ←

S3F80P5_UM_ REV1.00 INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b

INSTRUCTION SET S3F80P5_UM_ REV1.00 CALL — Call Procedure CALL dst Operation: SP ← SP – 1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ← dst The current

S3F80P5_UM_ REV1.00 INSTRUCTION SET CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1&qu

List of Tables Table Title Page Number Number 1-1 Pin Descriptions of 24-SOP/SDIP...

INSTRUCTION SET S3F80P5_UM_ REV1.00 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0". Fla

S3F80P5_UM_ REV1.00 INSTRUCTION SET COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complement

INSTRUCTION SET S3F80P5_UM_ REV1.00 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destin

S3F80P5_UM_ REV1.00 INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC

INSTRUCTION SET S3F80P5_UM_ REV1.00 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst – src "0",

S3F80P5_UM_ REV1.00 INSTRUCTION SET DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4-bit BC

INSTRUCTION SET S3F80P5_UM_ REV1.00 DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working

S3F80P5_UM_ REV1.00 INSTRUCTION SET DEC — Decrement DEC dst Operation: dst ← dst – 1 The contents of the destination operand are decremented by

INSTRUCTION SET S3F80P5_UM_ REV1.00 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (which mu

S3F80P5_UM_ REV1.00 INSTRUCTION SET DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cl

List of Tables(Conclude) Table Title Page Number Number 18-1 Descriptions of Pins Used to Read/Write the Flash ROM...

INSTRUCTION SET S3F80P5_UM_ REV1.00 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QU

S3F80P5_UM_ REV1.00 INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst Th

INSTRUCTION SET S3F80P5_UM_ REV1.00 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets bit zero of the system mode regist

S3F80P5_UM_ REV1.00 INSTRUCTION SET ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is us

INSTRUCTION SET S3F80P5_UM_ REV1.00 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful whe

S3F80P5_UM_ REV1.00 INSTRUCTION SET IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock

INSTRUCTION SET S3F80P5_UM_ REV1.00 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented b

S3F80P5_UM_ REV1.00 INSTRUCTION SET INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be a

INSTRUCTION SET S3F80P5_UM_ REV1.00 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast)Operation: FLAGS ← @SP PC ↔ IP SP ← SP + 1 F

S3F80P5_UM_ REV1.00 INSTRUCTION SET JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst The cond

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW S3C8/S3F8-SERIES MICROCONTROLLERS Samsung's S3C8/S3F8-series of 8-bit single-chip CMOS

INSTRUCTION SET S3F80P5_UM_ REV1.00 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition specified by t

S3F80P5_UM_ REV1.00 INSTRUCTION SET LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The so

INSTRUCTION SET S3F80P5_UM_ REV1.00 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H

S3F80P5_UM_ REV1.00 INSTRUCTION SET LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specifi

INSTRUCTION SET S3F80P5_UM_ REV1.00 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruction loads a byte from program or dat

S3F80P5_UM_ REV1.00 INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; P

INSTRUCTION SET S3F80P5_UM_ REV1.00 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← src rr ← rr – 1 These instruct

S3F80P5_UM_ REV1.00 INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ← src rr ← rr + 1 These instru

INSTRUCTION SET S3F80P5_UM_ REV1.00 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation: rr ← rr – 1 dst ← src Th

S3F80P5_UM_ REV1.00 INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr ← rr + 1 dst ← src Th

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 FEATURES CPU • SAM8 RC CPU core Memory • Program memory: - 18-Kbyte Internal Flash Memory - 10 years data r

INSTRUCTION SET S3F80P5_UM_ REV1.00 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the des

S3F80P5_UM_ REV1.00 INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand (even re

INSTRUCTION SET S3F80P5_UM_ REV1.00 NEXT — Next NEXT Operation: PC ← @ IP IP ← IP + 2 The NEXT instruction is useful when implementing thr

S3F80P5_UM_ REV1.00 INSTRUCTION SET NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, on

INSTRUCTION SET S3F80P5_UM_ REV1.00 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the des

S3F80P5_UM_ REV1.00 INSTRUCTION SET POP — Pop From Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed

INSTRUCTION SET S3F80P5_UM_ REV1.00 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction i

S3F80P5_UM_ REV1.00 INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instructio

INSTRUCTION SET S3F80P5_UM_ REV1.00 PUSH — Push To Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements the stac

S3F80P5_UM_ REV1.00 INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instructi

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW BLOCK DIAGRAM (24-PIN PACKAGE) Figure 1-1. Block Diagram (24-pin) 1-3

INSTRUCTION SET S3F80P5_UM_ REV1.00 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instruct

S3F80P5_UM_ REV1.00 INSTRUCTION SET RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its

INSTRUCTION SET S3F80P5_UM_ REV1.00 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the

S3F80P5_UM_ REV1.00 INSTRUCTION SET RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6

INSTRUCTION SET S3F80P5_UM_ REV1.00 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n

S3F80P5_UM_ REV1.00 INSTRUCTION SET RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6

INSTRUCTION SET S3F80P5_UM_ REV1.00 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1),

S3F80P5_UM_ REV1.00 INSTRUCTION SET SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS r

INSTRUCTION SET S3F80P5_UM_ REV1.00 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS reg

S3F80P5_UM_ REV1.00 INSTRUCTION SET SBC — Subtract With Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with th

Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. S

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN ASSIGNMENTS VssXinXoutTESTSDAT/P0.0/INT0SCLK/P0.1/INT1nRESET/P0.2/INT2P0.3/INT3P0.4/INT4P0.5/INT4P0.6/INT

INSTRUCTION SET S3F80P5_UM_ REV1.00 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previou

S3F80P5_UM_ REV1.00 INSTRUCTION SET SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1

INSTRUCTION SET S3F80P5_UM_ REV1.00 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) =

S3F80P5_UM_ REV1.00 INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and

INSTRUCTION SET S3F80P5_UM_ REV1.00 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destinati

S3F80P5_UM_ REV1.00 INSTRUCTION SET SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits

INSTRUCTION SET S3F80P5_UM_ REV1.00 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected

S3F80P5_UM_ REV1.00 INSTRUCTION SET TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destin

INSTRUCTION SET S3F80P5_UM_ REV1.00 WFI — Wait For Interrupt WFI Operation: The CPU is effectively halted until an interrupt occurs, except that

S3F80P5_UM_ REV1.00 INSTRUCTION SET XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logically excl

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW Table 1-1. Pin Descriptions of 24-SOP/SDIP Pin Names Pin Type Pin Description CircuitType 28 Pin No. Shared Fu

INSTRUCTION SET S3F80P5_UM_ REV1.00 NOTES 6-88

S3F80P5_UM_ REV1.00 CLOCK AND POWER CIRCUITS 7 CLOCK AND POWER CIRCUITS OVERVIEW The clock frequency for the S3F80P5 can be generated by an extern

CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1.00 XINXOUTC1C2 Figure 7-1. Main Oscillator Circuit (External Crystal or Ceramic Resonator) XINXOUTExterna

S3F80P5_UM_ REV1.00 CLOCK AND POWER CIRCUITS CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the sys

CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1.00 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in addres

S3F80P5_UM_ REV1.00 CLOCK AND POWER CIRCUITS VDDVDDR 1C 1 C 2 Figure 7-5. Power Circuit (VDD) Typically, application systems have a resister and tw

CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1.00 NOTES 7-6

S3F80P5_UM_ REV1.00 RESET 8 RESET OVERVIEW Resetting the MCU is the function to start processing by generating reset signal using several reset

RESET S3F80P5_UM_ REV1.00 Watchdog Timer STOP(EI)external interrupt enableP0&P2.0 (INT0-INT5)STOPLVDIPORP0RESET12345RESET Contorl Bit '1&ap

S3F80P5_UM_ REV1.00 RESET P0&P2.0(INT0~INT5)NoiseFilterExternal InterruptControl BlockP0& P2.0EnabledINT0~INT5SED&RCircuitP0STOPSTOPCO

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS VDDPull-upEnableVDDINPUT/OUTPUTPull-UpResistor(67kΩ- typ)DataVSSExternalInterruptOutput DisableNo

RESET S3F80P5_UM_ REV1.00 RESET MECHANISM The interlocking work of reset pin and LVD circuit supplies two operating modes: back-up mode input, and s

S3F80P5_UM_ REV1.00 RESET INTERNAL POWER-ON RESET The power-on reset circuit is built on the S3F80P5 product. When power is initially applied to t

RESET S3F80P5_UM_ REV1.00 Normal Operating Mode (LVD on)VDDVLVDtWAIT(4096x16x1/fosc)VPORPOR Reset ReleaseInternal ResetReleaseLVD ResetReleaseStop M

S3F80P5_UM_ REV1.00 RESET STOP ERROR DETECTION & RECOVERY When RESET Control Bit (smart option bit [0] @ 03FH) is set to ‘0’ and chip is in sto

RESET S3F80P5_UM_ REV1.00 POWER-DOWN MODES The power down mode of S3F80P5 are described following that: — Idle mode — Back- up mode — Stop mode IDL

S3F80P5_UM_ REV1.00 RESET BACK-UP MODE For reducing current consumption, S3F80P5 goes into Back-up mode. If a falling level of VDD is detected by L

RESET S3F80P5_UM_ REV1.00 Normal Operating ModeVDDVLVDtWAITVPORStop Mode (LVD off)Key-inNormal Operating ModeVDDVLVDtWAITVPORStop Mode (LVD off)Key

S3F80P5_UM_ REV1.00 RESET STOP MODE STOP mode is invoked by executing the instruction ‘STOP’, after setting the stop control register (STOPCON). In

RESET S3F80P5_UM_ REV1.00 SOURCES TO RELEASE STOP MODE Stop mode is released when following sources go active: — System Reset by Internal Power-On

S3F80P5_UM_ REV1.00 RESET SED&R (Stop Error Detect and Recovery) The Stop Error Detect & Recovery circuit is used to release stop mode and

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW PIN CIRCUITS (Continued) VDDPull-upResistor(67kΩ-Typ)VDDVSSNoiseFilter INPUT/OUTPUTPull-upEnableDataOutput Disa

RESET S3F80P5_UM_ REV1.00 SYSTEM RESET OPERATION System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initial

S3F80P5_UM_ REV1.00 RESET HARDWARE RESET VALUES Tables 8-2 list the reset values for CPU and system registers, peripheral control registers, and pe

RESET S3F80P5_UM_ REV1.00 Table 8-2. Set 1, Bank 0 Register Values After Reset (Continued) Address Bit Values After Reset Register Name MnemonicDe

S3F80P5_UM_ REV1.00 RESET Table 8-3. Set 1, Bank 1 Register Values After Reset Address Bit Values After Reset Register Name MnemonicDec Hex 7 6

RESET S3F80P5_UM_ REV1.00 Table 8-4. Reset Generation According to the Condition of Smart Option Smart option 1st bit @3FH Mode Reset Source 1 0 Wat

S3F80P5_UM_ REV1.00 RESET RECOMMENDATION FOR UNUSUED PINS To reduce overall power consumption, please configure unused pins according to the guidel

RESET S3F80P5_UM_ REV1.00 SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS For more understanding, please see the below description Table

S3F80P5_UM_ REV1.00 I/O PORTS 9 I/O PORTS OVERVIEW The S3F80P5 microcontroller has four bit-programmable I/O ports, P0, P1, P2, P3. Two ports, P0 a

I/O PORTS S3F80P5_UM_ REV1.00 Table 9-1. S3F80P5 Port Configuration Overview (24-SOP) Port Configuration Options Port 0 8-bit general-purpose I/O

S3F80P5_UM_ REV1.00 I/O PORTS PORT DATA REGISTERS Table 9-4 gives you an overview of the register locations of all four S3F80P5 I/O port data regis

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS (Continued) DataOutput DisableOpen-DrainVDDPull-upEnableVDDINPUT/OUTPUTPull-UpResistor(67kΩ- typ

I/O PORTS S3F80P5_UM_ REV1.00 PULL-UP RESISTOR ENABLE REGISTERS You can assign pull-up resistors to the pin circuits of individual pins in port0 an

S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 10 BASIC TIMER and TIMER 0 OVERVIEW The S3F80P5 has two default timers: the 8-bit basic timer and the

BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the inp

S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watch-dog Timer Function You can program the basic timer overflow sign

BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 TIMER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to — Select the timer 0

S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 Timer 0 Control Register (T0CON)D2H, Set 1, Bank0 , R/W.7 .6 .5 .4 .3 .2 .1 .0MSBLSB Timer 0 Interrupt

BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors FAH and FCH) The timer 0 module can gene

S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of

BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 Capture Mode In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads th

S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 MUXMUXDIVR8-Bit Up-Counter(T0CNT)8-Bit CompatatorTimer0 BufferRegisterBits 5, 4Bit 0Bit 1IRQ0ClearData

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW PIN CIRCUITS (Continued) VDDPull-upEnable P3.0/T0PWM/T0CAP/ T1CAP/T2CAP Pull-upResistor(67kΩ-Typ)Open-DrainPort

BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00  PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to

S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0  PROGRAMMING TIP — Programming Timer 0 This sample program sets timer 0 to interval timer mode, sets t

BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00  PROGRAMMING TIP — Programming Timer 0 (Continued) CP R0,#32H ; 50 × 4 = 200 ms JR ULT,

S3F80P5_UM_ REV1.00 TIMER 1 11 TIMER 1 OVERVIEW The S3F80P5 microcontroller has a 16-bit timer/counter called Timer 1 (T1). For universal remote co

TIMER 1 S3F80P5_UM_ REV1.00 TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflo

S3F80P5_UM_ REV1.00 TIMER 1 TIMER 1 MATCH INTERRUPT Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit c

TIMER 1 S3F80P5_UM_ REV1.00 MUX16-Bit Up-Counter(Read-Only)16-Bit CompatatorTimer 1 High/LowBuffer RegisterMUXIRQ1ClearIRQ1Match(note) NOTE:Match

S3F80P5_UM_ REV1.00 TIMER 1 TIMER 1 CONTROL REGISTER (T1CON) The Timer 1 control register, T1CON, is located in Set 1, FAH, Bank0 and is read/write

TIMER 1 S3F80P5_UM_ REV1.00 Timer1 Counter High-byte Register (T1CNTH)F6H, Set 1, Bank 0, R.7 .6 .5 .4 .3 .2 .1 .0MSB LSBReset Value: 00HTimer 1 C

S3F80P5_UM_ REV1.00 COUNTER A 12 COUNTER A OVERVIEW The S3F80P5 microcontroller has one 8-bit counter called counter A. Counter A, which can be use

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS (Continued) VDDPull-upEnableVDD P3.1/REM/T0CKPull-upResistor(67kΩ-Typ)Open-DrainPort 3.1 DataVSSP

COUNTER A S3F80P5_UM_ REV1.00 MUX 8-Bit Down CounterMUXCounter A DataLow Byte RegisterIRQ2(CAINT) NOTE:The value of the CADATAL register is loaded

S3F80P5_UM_ REV1.00 COUNTER A COUNTER A CONTROL REGISTER (CACON) The counter A control register, CACON, is located in F3H, Set 1, Bank 0, and is re

COUNTER A S3F80P5_UM_ REV1.00 COUNTER A PULSE WIDTH CALCULATIONS tLOWtHIGHtLOW To generate the above repeated waveform consisted of low period ti

S3F80P5_UM_ REV1.00 COUNTER A HighHighCounter A Clock0HCAOF = '0'CADATAL = 01-FFHCADATAH = 00HCAOF = '0'CADATAL = 00HCADATAH =

COUNTER A S3F80P5_UM_ REV1.00  PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1 This example sets Counter A to the repeat mode, s

S3F80P5_UM_ REV1.00 COUNTER A  PROGRAMMING TIP — To generate a one-pulse signal through P3.1 This example sets Counter A to the one shot mode, set

COUNTER A S3F80P5_UM_ REV1.00 NOTES 12-8

S3F80P5_UM_ REV1.00 TIMER 2 13 TIMER 2 OVERVIEW The S3F80P5 microcontroller has a 16-bit timer/counter called Timer 2 (T2). For universal remote co

TIMER 2 S3F80P5_UM_ REV1.00 TIMER 2 OVERFLOW INTERRUPT Timer 2 can be programmed to generate an overflow interrupt (IRQ3, F0H) whenever an overflow

S3F80P5_UM_ REV1.00 TIMER 2 TIMER 2 MATCH INTERRUPT Timer 2 can also be used to generate a match interrupt (IRQ3, vector F2H) whenever the 16-bit c

S3F80P5_UM_ REV1.00 ADDRESS SPACE 2 ADDRESS SPACE OVERVIEW The S3F80P5 microcontroller has two types of address space: — Internal program memory (

TIMER 2 S3F80P5_UM_ REV1.00 MUX16-Bit Up-Counter(Read-Only)16-Bit CompatatorTimer 2 High/LowBuffer RegisterMUXIRQ3ClearIRQ3Match (note) NOTE:Match

S3F80P5_UM_ REV1.00 TIMER 2 TIMER 2 CONTROL REGISTER (T2CON) The timer 2 control register, T2CON, is located in address E8H, Bank1, Set 1 and is re

TIMER 2 S3F80P5_UM_ REV1.00 Timer2 Counter High-Byte Register (T2CNTH)E4H , Set 1, Bank 1, Read-only.7 .6 .5 .4 .3 .2 .1 .0MSB LSBReset Value: 00HT

S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE 14 EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F80P5 has an on-chip flash memory internally

EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 User Program Mode This mode supports sector erase, byte programming, byte read and one protecti

S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE SMART OPTION Smart option is the program memory option for starting condition of the chip. The

EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the av

S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) FLASH MEMORY CONTROL REGISTER (FMCON) FMCON

EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for the erase or

S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE SECTOR ERASE User can erase a flash memory partially by using sector erase function only in use

ADDRESS SPACE S3F80P5_UM_ REV1.00 PROGRAM MEMORY Program memory stores program code or table data. The S3F80P5 has 18-Kbyte of internal programma

EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Re

S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE  PROGRAMMING TIP — Sector Erase Case1. Erase one sector • • ERASE_ONESECTOR:

EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 SECTOR_ERASE: LD R12,SecNumH LD R14,SecNumL

S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING A flash memory is programmed in one-byte unit after sector erase. The write operat

EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 SB1Start; Select Bank1; User Program Mode Enable; Set Secotr Base Address; Write data at fla

S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE SB1Start; Select Bank1; User Program Mode Enable; Set Secotr Base Address; Write data at fla

EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00  PROGRAMMING TIP — Programming Case1. 1-byte programming • • WR_BYTE: ; Wr

S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE Case3. Programming to the flash memory space located in other sectors • • WR_INSECTOR2:

EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 READING The read operation starts by ‘LDC’ instruction. The program procedure in user program

S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE HARD LOCK PROTECTION User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4. This fun

S3F80P5_UM_ REV1.00 ADDRESS SPACE SMART OPTION Smart option is the program memory option for starting condition of the chip. The program memory addr

EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 NOTES 14-18

S3F80P5_UM_ REV1.00 LOW VOLTAGE DETECTOR 15 LOW VOLTAGE DETECTOR OVERVIEW The S3F80P5 micro-controller has a built-in Low Voltage Detector (LVD) c

LOW VOLTAGE DETECTOR S3F80P5_UM_ REV1.00 NOTES 1. A term of LVD is a symbol of parameter that means ‘Low Level Detect Voltage for Back-Up Mode’.

S3F80P5_UM_ REV1.00 LOW VOLTAGE DETECTOR LOW VOLTAGE DETECTOR CONTROL REGISTER (LVDCON) LVDCON.0 is used flag bit to indicate low battery in IR ap

S3F80P5_UM_ REV1.00 ELECTRICAL DATA 16 ELECTRICAL DATA OVERVIEW In this section, S3F80P5 electrical characteristics are presented in tables and g

ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating *TBD Unit Supply Voltag

S3F80P5_UM_ REV1.00 ELECTRICAL DATA Table 16-2. D.C. Electrical Characteristics (Continued) (TA = -25 °C to + 85 °C, VDD = 1.60 V to 3.6 V) Par

ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-2. D.C. Electrical Characteristics (Continued) (TA = -25 °C to + 85 °C, VDD = 1.60 V to 3.6 V) Para

S3F80P5_UM_ REV1.00 ELECTRICAL DATA NOTE: The voltage gaps (LVD_GAPn (n=1~4)) between LVD and LVD FLAGn(n=1~4) have ± 80mV distribution. LVD and

ELECTRICAL DATA S3F80P5_UM_ REV1.00 Execution ofSTOP Instrction~~VDDDR~~Stop ModeIdle Mode(Basic Timer Active)Data Retention ModetWAITEXT INTVDDNo

Preface The S3F80P5 Microcontroller User's Manual is designed for application designers and programmers who are using the S3F80P5 microcontrolle

ADDRESS SPACE S3F80P5_UM_ REV1.00 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP

S3F80P5_UM_ REV1.00 ELECTRICAL DATA Normal Operating ModeStop ModeOscillation Stabilization TimeResetOccurExecution ofSTOP InstrctionVDDNOTE:tWAIT

ELECTRICAL DATA S3F80P5_UM_ REV1.00 tINTHtINTL0.8 VDD0.2 VDD0.2 VDD0.8 VDDNOTE:The unit tCPU means one CPU clock period. Figure 16-3. Input Timing

S3F80P5_UM_ REV1.00 ELECTRICAL DATA Table 16-8. Oscillation Characteristics (TA = -25 °C to + 85 °C) Oscillator Clock Circuit Conditions Min T

ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-9. Oscillation Stabilization Time (TA = -25 °C to + 85 °C, VDD = 3.6 V) Oscillator Test Condition Mi

S3F80P5_UM_ REV1.00 ELECTRICAL DATA Minimun InstructionClock1kHzfOSC(Main Oscillator Frequency)12345Supply Voltage (V)Minimun Instruction Clock =

ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-11. ESD Characteristics Parameter Symbol Conditions Min Typ Max Unit HBM 2000 − − V MM 200 − − V El

S3F80P5_UM_ REV1.00 MECHANICAL DATA 17 MECHANICAL DATA OVERVIEW The S3F80P5 micro-controller is currently available in a 24-pin SOP and SDIP packag

MECHANICAL DATA S3F80P5_UM_ REV1.00 NOTE: Dimensions are in millimeters.23.35 MAX22.95 ± 0.20(1.70)24-SDIP-3006.40 ± 0.20#24#10.46 ± 0.100.89 ±

S3F80P5_UM_ REV1.00 S3F80P5 FLASH MCU 18 S3F80P5 FLASH MCU OVERVIEW The S3F80P5 single-chip CMOS microcontroller is the Flash MCU. It has an on-chip

S3F80P5 FLASH MCU S3F80P5_UM_ REV1.00 VssXinXoutTESTSDAT/P0.0/INT0SCLK/P0.1/INT1nRESET/P0.2/INT2P0.3/INT3P0.4/INT4P0.5/INT4P0.6/INT4P0.7/INT4S3C80P5

S3F80P5_UM_ REV1.00 ADDRESS SPACE REGISTER ARCHITECTURE In the S3F80P5 implementation, the upper 64-byte area of register files is expanded two 64-b

S3F80P5_UM_ REV1.00 S3F80P5 FLASH MCU Table 18-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin N

S3F80P5 FLASH MCU S3F80P5_UM_ REV1.00 OPERATING MODE CHARACTERISTICS When 3.3 V is supplied to the TEST pin of the S3F80P5, the Flash ROM programming

S3F80P5_UM_ REV1.00 ELECTRICAL DATA 19 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system on a tur

DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 [Development System Configuration] BusEmulator [ SK-1200(RS-232,USB) or OPENIce I-500(RS-232) ]R

S3F80P5_UM_ REV1.00 ELECTRICAL DATA TB80PB TARGET BOARD The TB80PB target board can be used for development of S3F80P5. The TB80PB target board is

DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 Table 19-1. Setting of the Jumper in TB80PB JP# Description 1-2 Connection 2-3 Connection Default Setting

S3F80P5_UM_ REV1.00 ELECTRICAL DATA – STOP LED This LED is ON when the evaluation chip (S3E80PB) is in stop mode. 19-5

DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 NOTE:N.C means No Connection.J21234567891011121314151617181920444342414039383736353433323130292827262521 2422

S3F80P5_UM_ REV1.00 ELECTRICAL DATA Third Parties for Development Tools SAMSUNG provides a complete line of development tools for SAMSUNG's m

DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 OTP/MTP PROGRAMMER (WRITER) SPW-uni Single OTP/ MTP/FLASH Programmer • Download/Upload and data edit functio

ADDRESS SPACE S3F80P5_UM_ REV1.00 Bank1D0HCFHE0HDFHC0HBank 0System andPeripheralControl Register(Register AddressingMode)System Register(Register

S3F80P5_UM_ REV1.00 ELECTRICAL DATA OTP/MTP PROGRAMMER (WRITER) (Continued) US-pro Portable Samsung OTP/MTP/FLASH Programmer • Portable Samsung

DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 NOTES 19-10

S3F80P5_UM_ REV1.00 ADDRESS SPACE REGISTER PAGE POINTER (PP) The S3C8/S3F8-series architecture supports the logical expansion of the physical 333-by

ADDRESS SPACE S3F80P5_UM_ REV1.00 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 3

S3F80P5_UM_ REV1.00 ADDRESS SPACE PRIME REGISTER SPACE The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) are called the

ADDRESS SPACE S3F80P5_UM_ REV1.00 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit

S3F80P5_UM_ REV1.00 ADDRESS SPACE USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to s

ADDRESS SPACE S3F80P5_UM_ REV1.00 16-byte non-contiguousworking register blockRegister FileContains 328-Byte Slices8-Byte Slice00H (R0)07H (R15)F

S3F80P5_UM_ REV1.00 ADDRESS SPACE REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register address

Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8/S3F8-Series Microcontrollers...

ADDRESS SPACE S3F80P5_UM_ REV1.00 FFHD0HFFHC0HSet 2CFHRP1RP0RegisterPointersC0HBFH00HSpecial-Purpose Registers General-Purpose RegistersAllAddres

S3F80P5_UM_ REV1.00 ADDRESS SPACE COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byt

ADDRESS SPACE S3F80P5_UM_ REV1.00  PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should acce

S3F80P5_UM_ REV1.00 ADDRESS SPACE Together they create an8-bit register addressRegister pointerprovides fivehigh-order bitsAddressOPCODESelectsRP0 o

ADDRESS SPACE S3F80P5_UM_ REV1.00 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a s

S3F80P5_UM_ REV1.00 ADDRESS SPACE Specifies workingregister addressingRP0Selects RP1RP101 1 10 1 1001 1 1 0 0 000 1 1 1 0 0 0 0Register address (0AB

ADDRESS SPACE S3F80P5_UM_ REV1.00 SYSTEM AND USER STACKS S3C8-series microcontrollers use the system stack for subroutine calls and returns and t

S3F80P5_UM_ REV1.00 ADDRESS SPACE  PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform s

ADDRESS SPACE S3F80P5_UM_ REV1.00 NOTES 2-22

S3F80P5_UM_ REV1.00 ADDRESSING MODES 3 ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memor

Table of Contents (Continued) Chapter 3 Addressing Modes Overview ...

ADDRESSING MODES S3F80P5_UM_ REV1.00 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register

S3F80P5_UM_ REV1.00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified

ADDRESSING MODES S3F80P5_UM_ REV1.00 INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODEPoints toRegister PairExampleInstructionReferencesPro

S3F80P5_UM_ REV1.00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODEADDRESS4-bitWorkingRegisterAddressPoint to theWoking Re

ADDRESSING MODES S3F80P5_UM_ REV1.00 INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODE4-bit WorkingRegister AddressSample Instructions:LCD

S3F80P5_UM_ REV1.00 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruct

ADDRESSING MODES S3F80P5_UM_ REV1.00 INDEXED ADDRESSING MODE (Continued) Register FileOPERANDProgram MemoryorData MemoryPoint to WorkingRegister

S3F80P5_UM_ REV1.00 ADDRESSING MODES INDEXED ADDRESSING MODE (Continued) Register FileOPERANDProgram MemoryorData MemoryPoint to WorkingRegister Pa

ADDRESSING MODES S3F80P5_UM_ REV1.00 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit mem

S3F80P5_UM_ REV1.00 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) OPCODEProgram MemoryLower Address ByteProgramMemoryAddressUsedUpper Address By

Table of Contents(Continued) Chapter 6 Instruction Set Overview...

ADDRESSING MODES S3F80P5_UM_ REV1.00 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in th

S3F80P5_UM_ REV1.00 ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between

ADDRESSING MODES S3F80P5_UM_ REV1.00 IMMEDIATE MODE (IM) In Immediate (IM) mode, the operand value used in the instruction is the value supplied

S3F80P5_UM_ REV1.00 CONTROL REGISTERS 4 CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3F80P5 control registers are pres

CONTROL REGISTERS S3F80P5_UM_ REV1.00 Table 4-1. Mapped Registers (Bank0, Set1) Register Name Mnemonic Decimal Hex R/W Timer 0 Counter T0CNT 2

S3F80P5_UM_ REV1.00 CONTROL REGISTERS Table 4-1. Mapped Registers (Continued) Register Name Mnemonic Decimal Hex R/W Counter A Control Register

CONTROL REGISTERS S3F80P5_UM_ REV1.00 Table 4-2. Mapped Registers (Bank1, Set1) Register Name Mnemonic Decimal Hex R/W LVD Control Register LVD

S3F80P5_UM_ REV1.00 CONTROL REGISTERS FLAGS - System Flags RegisterBit IdentifierReset ValueRead/WriteR = Read-onlyW = Write-onlyR/W = Read/write&a

CONTROL REGISTERS S3F80P5_UM_ REV1.00 BTCON — Basic Timer Control Register D3H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset

S3F80P5_UM_ REV1.00 CONTROL REGISTERS CACON — Counter A Control Register F3H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va

Table of Contents (Continued) Part II Hardware Descriptions Chapter 9 I/O Ports Overview ...

CONTROL REGISTERS S3F80P5_UM_ REV1.00 CLKCON — System Clock Control Register D4H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset

S3F80P5_UM_ REV1.00 CONTROL REGISTERS EMT — External Memory Timing Register (NOTE) FEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Res

CONTROL REGISTERS S3F80P5_UM_ REV1.00 FLAGS — System Flags Register D5H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x

S3F80P5_UM_ REV1.00 CONTROL REGISTERS FMCON — Flash Memory Control Register EFH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Re

CONTROL REGISTERS S3F80P5_UM_ REV1.00 FMSECH — Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3

S3F80P5_UM_ REV1.00 CONTROL REGISTERS IMR — Interrupt Mask Register DDH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x

CONTROL REGISTERS S3F80P5_UM_ REV1.00 IPH — Instruction Pointer (High Byte) DAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset

S3F80P5_UM_ REV1.00 CONTROL REGISTERS IPR — Interrupt Priority Register FFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x

CONTROL REGISTERS S3F80P5_UM_ REV1.00 IRQ — Interrupt Request Register DCH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0

S3F80P5_UM_ REV1.00 CONTROL REGISTERS LVDCON — LVD Control Register E0H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value −

Table of Contents (Continued) Chapter 12 Counter A Overview...

CONTROL REGISTERS S3F80P5_UM_ REV1.00 LVDSEL — LVD Flag Level Selection Register F1H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Res

S3F80P5_UM_ REV1.00 CONTROL REGISTERS P0CONH — Port 0 Control Register (High Byte) E8H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

CONTROL REGISTERS S3F80P5_UM_ REV1.00 P0CONL — Port 0 Control Register (Low Byte) E9H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Re

S3F80P5_UM_ REV1.00 CONTROL REGISTERS P0INT — Port 0 External Interrupt Enable Register F1H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

CONTROL REGISTERS S3F80P5_UM_ REV1.00 P0PND — Port 0 External Interrupt Pending Register F2H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F80P5_UM_ REV1.00 CONTROL REGISTERS P0PUR — Port 0 Pull-up Resistor Enable Register E7H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0

CONTROL REGISTERS S3F80P5_UM_ REV1.00 P1CONH — Port 1 Control Register (High Byte) EAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Re

S3F80P5_UM_ REV1.00 CONTROL REGISTERS P1CONL — Port 1 Control Register (Low Byte) EBH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Res

CONTROL REGISTERS S3F80P5_UM_ REV1.00 P1OUTPU — Port 1 Output Pull-up Resistor Enable Register F2H Set1 Bank1 Bit Identifier .7 .6 .5 .

S3F80P5_UM_ REV1.00 CONTROL REGISTERS P2CONL — Port 2 Control Register (Low Byte) EDH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Res

Table of Contents (Conclude) Chapter 15 Lower Voltage Detector Overview ...

CONTROL REGISTERS S3F80P5_UM_ REV1.00 P2INT — Port 2 External Interrupt Enable Register E5H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F80P5_UM_ REV1.00 CONTROL REGISTERS P2OUTMD — Port 2 Output Mode Selection Register F3H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 R

CONTROL REGISTERS S3F80P5_UM_ REV1.00 P2PND — Port 2 External Interrupt Pending Register E6H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F80P5_UM_ REV1.00 CONTROL REGISTERS P2PUR — Port 2 Pull-up Resistor Enable Register EEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0

CONTROL REGISTERS S3F80P5_UM_ REV1.00 P3CON — Port 3 Control Register EFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu

S3F80P5_UM_ REV1.00 CONTROL REGISTERS NOTES: 1. The port 3 data register, P3, at location E3H, set1, bank0, contains seven bit values which corres

CONTROL REGISTERS S3F80P5_UM_ REV1.00 P3OUTPU — Port 3 Output Pull-up Resistor Enable Register F4H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2

S3F80P5_UM_ REV1.00 CONTROL REGISTERS PP — Register Page Pointer DFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0

CONTROL REGISTERS S3F80P5_UM_ REV1.00 RESETID — Reset Source Indicating Register F0H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Rea

S3F80P5_UM_ REV1.00 CONTROL REGISTERS RP0 — Register Pointer 0 D6H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 1 1 0 0 0