Samsung M393T2950GZ3-CD5 Ficha Técnica

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 1 of 26DDR2 Registered SDRAM MODULE240pin Registered Module based on 512Mb G-die72-bit ECC60FBGA with Lead-Free and

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 10 of 26A0Serial PDA1 A2SA0 SA1 SA2SCLSDAVSSD0 - D35VDD/VDDQD0 - D35D0 - D35VREFVDDSPDSerial PDWPPLLOECK0CK0RESETPCK

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 11 of 26Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 12 of 26VDDQVIH(AC) minVIH(DC) minVREFVIL(DC) maxVIL(AC) maxVSS< AC Input Test Signal Waveform >VSWING(MAX)del

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 13 of 26(IDD values are for full operating range of Voltage and Temperature)Symbol Proposed Conditions Units NoteIDD

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 14 of 26 (TA=0oC, VDD= 1.9V)* Module IDD was calculated on the basis of component IDD and can be differently measu

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 15 of 26(TA=0oC, VDD= 1.9V)* Module IDD was calculated on the basis of component IDD and can be differently measur

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 16 of 26(TA=0oC, VDD= 1.9V)* Module IDD was calculated on the basis of component IDD and can be differently measur

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 17 of 26(TA=0oC, VDD= 1.9V)* Module IDD was calculated on the basis of component IDD and can be differently measur

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 18 of 26 (VDD=1.8V, VDDQ=1.8V, TA=25oC)* DM is internally loaded to match DQ and DQS identically.ParameterSymbolMin

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 19 of 26(Refer to notes for informations related to this table at the component datasheet)Parameter SymbolDDR2-800 D

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 2 of 261.0 DDR2 Registered DIMM Ordering Information ...

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 20 of 26Parameter SymbolDDR2-800 DDR2-667UnitsNotesmin max min maxFour Activate Window for 1KB page size products tF

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 21 of 26(Refer to notes for informations related to this table at the component datasheet)Parameter SymbolDDR2-533 D

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 22 of 26Parameter SymbolDDR2-533 DDR2-400Units Notesmin max min maxFour Activate Window for 1KB page size products t

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 23 of 26The used device is 64M x8 DDR2 SDRAM, FBGA.DDR2 SDRAM Part NO : K4T51083QGRegisterPLL1.27 ± 0.102.701.0 maxU

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 24 of 26The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA.DDR2 SDRAM Part NO : K4T51083QG / K4T51043QGRegisterPLL

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 25 of 26The used device is 128M x4 DDR2 SDRAM, FBGA.DDR2 SDRAM Part NO : K4T51043QGPLL1.27 ± 0.104.001.0 max1.7 max2

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 26 of 26CK0CK0PLLOUT1OUTNReg.AReg.BFeedback InFeedback OutIN0ns (nominal)C120 ohms120 ohms120 ohms120 ohmsCNote:1. T

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 3 of 26Revision HistoryRevision Month Year History1.0 July 2008 - Initial Release

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 4 of 26Note :1. “Z” of Part number(11th digit) stands for Lead-Free and RoHS compliant products.2. “3” of Part numbe

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 5 of 26NC = No Connect, RFU = Reserved for Future Use1. RESET (Pin 18) is connected to both OE of PLL and Reset of r

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 6 of 26Symbol Type FunctionCK0 Input Positive line of the differential pair of system clock inputs that drives input

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 7 of 26RS0DQS0DQS0DM0/DQS9NC/DQS9DM/RDQSNU/RDQSCS DQS DQSDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 8 of 26RS0DQS0DQS0DM0/DQS9NC/DQS9DM/RDQSNU/RDQSCS DQS DQSDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6

Rev. 1.0 July 2008DDR2 SDRAMRDIMM 9 of 26VSSRS0DQS0DQS0DM CS DQS DQSDQ0DQ1DQ2DQ3I/O 0I/O 1I/O 2I/O 3D0DM0/DQS9NC/DQS9DM CS DQS DQSDQ4DQ5DQ6DQ7I/O 0I/O