Samsung S3C8275X Manual do Utilizador

S3C8275X/F8275X/C8278X /F8278X/C8274X/F8274X 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER vii Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circu

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-30 P2PUR — Port 2 Pull-up Control Register ECH Set 1, Bank 0 Bit Identifier

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-31 P3CONH — Port 3 Control Register (High Byte) EDH Set 1, Bank 0 Bit Identifie

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-32 P3CONL — Port 3 Control Register (Low Byte) EEH Set 1, Bank 0 Bit Identif

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-33 P3PUR — Port 3 Pull-up Control Register EFH Set 1, Bank 0 Bit Identifier .

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-34 P4CONH — Port 4 Control Register (High Byte) E9H Set 1, Bank 1 Bit Identi

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-35 P4CONL — Port 4 Control Register (Low Byte) EAH Set 1, Bank 1 Bit Identifier

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-36 P5CONH — Port 5 Control Register (High Byte) EBH Set 1, Bank 1 Bit Identi

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-37 P5CONL — Port 5 Control Register (Low Byte) ECH Set 1, Bank 1 Bit Identifier

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-38 P6CON — Port 6 Control Register EDH Set 1, Bank 1 Bit Identifier .7 .6 .

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-39 PP — Register Page Pointer DFH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0

viii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER Table of Contents (Continued) Chapter 11 Timer 1 One 16-bit Timer Mode (Timer 1).

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-40 RP0 — Register Pointer 0 D6H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-41 SIOCON — SIO Control Register E1H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-42 SPH — Stack Pointer (High Byte) D8H Set 1 Bit Identifier .7 .6 .5 .4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-43 STPCON — Stop Control Register FBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-44 SYM — System Mode Register DEH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-45 TACON — Timer 1/A Control Register E6H Set 1, Bank 1 Bit Identifier .7 .6 .

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-46 TBCON — Timer B Control Register E7H Set 1, Bank 1 Bit Identifier .7 .6

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-47 WTCON — Watch Timer Control Register E1H Set 1, Bank 1 Bit Identifier .7 .6

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE 5-1 5 INTERRUPT STRUCTURE OVERVIEW The S3C8-series interrupt structure has three

INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-2 INTERRUPT TYPES The three components of the S3C8 interrupt structure des

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER ix Table of Contents (Continued) Chapter 16 Embedded Flash Memory Interface Overview.

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE 5-3 S3C8275X/C8278X/C8274X INTERRUPT STRUCTURE The S3C8275X/C8278X/C8274X microc

INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-4 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C827

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE 5-5 Table 5-1. Interrupt Vectors Vector Address Interrupt Source Request Rese

INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-6 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Inte

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE 5-7 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be co

INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-8 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there i

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE 5-9 SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is us

INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-10 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1,

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE 5-11 INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set

INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-12 Interrupt Priority Register (IPR)FFH, Set 1, Bank 0, R/W.7 .6 .5 .4 .3

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xi List of Figures Figure Title Page Number Number 1-1 Block Diagram ...

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE 5-13 INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt r

INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-14 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interr

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE 5-15 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servici

INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-16 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE 5-17 FAST INTERRUPT PROCESSING (Continued) Two other system registers support fa

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-1 6 INSTRUCTION SET OVERVIEW The SAM88RC instruction set is specifically design

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-2 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Inst

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-3 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instructi

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-4 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instructio

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-5 Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instructi

xii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER List of Figures Figure Title Page Number Number 5-1 S3C8-Series Interrupt Types...

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-6 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that descr

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1"

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-8 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-9 Table 6-4. Instruction Notation Conventions Notation Description Actual Ope

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-10 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) − 0 1 2 3

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-11 Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX)

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-12 CONDITION CODES The opcode of a conditional jump always contains a 4-bit fiel

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-13 INSTRUCTION DESCRIPTIONS This section contains detailed information and prog

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-14 ADC — Add with carry ADC dst,src Operation: dst ← dst + src + c The

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-15 ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xiii List of Figures (Continued) Page Title Page Number Number 9-19 Port 4 High-B

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-16 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-17 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0)

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-19 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instr

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-20 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction cle

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction se

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-22 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0)

xiv S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER List of Figures (Concluded) Page Title Page Number Number 17-1 Stop Mode Relea

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-26 CALL — Call Procedure CALL dst Operation: SP ← SP – 1 @SP ← PCL SP ← SP –

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-27 CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) i

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-28 CLR — Clear CLR dst Operation: dst ← "0" The destination locatio

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-29 COM — Complement COM dst Operation: dst ← NOT dst The contents of the

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-30 CP — Compare CP dst,src Operation: dst – src The source operand is compar

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-31 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation:

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-32 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operati

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-33 DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination opera

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-34 DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 con

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-35 DEC — Decrement DEC dst Operation: dst ← dst – 1 The contents of the dest

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xv List of Tables Table Title Page Number Number 1-1 S3C8275X/F8275X/C8278X/F8278X/C8

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system m

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-38 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER)

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-39 DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets b

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP +

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-43 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CP

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-44 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the des

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-45 INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents

xvi S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER List of Tables (Continued) Table Title Page Number Number 17-1 Absolute Maximum Ra

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-46 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS ←

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-47 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-48 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-49 LD — Load LD dst,src Operation: dst ← src The contents of the source are

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-50 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-51 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b)

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-52 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instructio

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-53 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-54 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← s

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-55 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ←

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapter 2: Address Spaces Usi

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-56 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation:

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-57 LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-58 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the sourc

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-59 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-60 NEXT — Next NEXT Operation: PC ← @ IP IP ← IP + 2 The NEXT instructi

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-61 NOP — No Operation NOP Operation: No action is performed when the CPU execu

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-62 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source oper

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-63 POP — Pop From Stack POP dst Operation: dst ← @SP SP ← SP + 1 The

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-64 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-65 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src

Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. S

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xix List of Register Descriptions Register Full Register Name Page Identifier Number

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-66 PUSH — Push To Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PU

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-67 PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-68 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-69 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is clear

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-70 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-71 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-72 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-73 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-74 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-75 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears t

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xxi List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Num

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-76 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-77 SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-78 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to lo

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-79 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ←

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-80 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation:

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-81 STOP — Stop Operation STOP Operation: The STOP instruction stops the both

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-82 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operan

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-83 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) T

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-84 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-85 TM — Test Under Mask TM dst,src Operation: dst AND src This instructio

xxii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER List of Instruction Descriptions (Continued) Instruction Full Register Name Page M

INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6-86 WFI — Wait for Interrupt WFI Operation: The CPU is effectively halted until

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET 6-87 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src T

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT 7-1 7 CLOCK CIRCUIT OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has two oscill

CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 7-2 MAIN OSCILLATOR CIRCUITS XINXOUT Figure 7-1. Crystal/Ceramic Oscillator (fx) XIN

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT 7-3 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle

CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 7-4 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT 7-5 CLOCK OUTPUT CONTROL REGISTER (CLOCON) The clock output control register, CLOCON,

CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 7-6 OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT 7-7 SWITCHING THE CPU CLOCK Data loading in the oscillator control register, OSCCON, d

CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 7-8 STOP Control Register (STPCON)FBH, Set 1, Bank 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RESET and POWER-DOWN 8-1 8 RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, t

RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-2 HARDWARE RESET VALUES Table 8-1, 8-2, 8-3 list the reset values for CPU a

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RESET and POWER-DOWN 8-3 Table 8-2. S3C8275X/C8278X/C8274X Set 1, Bank 0 Register Values After RE

RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-4 Table 8-3. S3C8275X/C8278X/C8274X Set 1, Bank 1 Register Values After RES

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RESET and POWER-DOWN 8-5 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP

RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-6 IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In i

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-1 9 I/O PORTS OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has seven bit-program

I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-2 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-3 PORT 0 Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins a

I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-4 Port 0 Control Register, High Byte (P0CONH)E4H, Set 1, Bank 0, R/W.7 .6 .5 .4

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1-2 FEATURESCPU • SAM88RC CPU core Memory • Program Memory(ROM) - 16K×8 bits progr

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-5 Port 0 Pull-up Control Register (P0PUR)E6H, Set 1, Bank 0, R/W.7 .6 .5 .4 .3 .2 .1 .0

I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-6 External Interrupt Pending Register (EXTIPND)F7H, Set 1, Bank 0, R/W.7 .6 .5 .

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-7 PORT 1 Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins a

I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-8 Port 1 Control Register, High Byte (P1CONH)E7H, Set 1, Bank 0, R/W.7 .6 .5 .4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-9 Port 1 Pull-up Control Register (P1PUR)E9H, Set 1, Bank 0, R/W.7 .6 .5 .4 .3 .2 .1 .0

I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-10 External Interrupt Control Register, Low Byte (EXTICONL)F9H, Set 1, Bank 0, R

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-11 PORT 2 Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins

I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-12 Port 2 Control Register, Low Byte (P2CONL)EBH, Set 1, Bank 0, R/W.7 .6 .5 .4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-13 PORT 3 Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins

I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-14 Port 3 Control Register, Low Byte (P3CONL)EEH, Set 1, Bank 0, R/W.7 .6 .5 .4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM 544/288 ByteRegister File16/8/4-KbyteROM8-Bit Timer/Counter BI/O Po

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-15 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins

I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-16 Port 4 Control Register, Low Byte (P4CONL)EAH, Set 1, Bank 1, R/W.7 .6 .5 .4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-17 PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins

I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-18 Port 5 Control Register, Low Byte (P5CONL)ECH, Set 1, Bank 1, R/W.7 .6 .5 .4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS 9-19 PORT 6 Port 6 is a 4-bit I/O port with individually configurable pins. Port 6 pins a

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BASIC TIMER 10-1 10 BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: •

BASIC TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 10-2 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, i

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BASIC TIMER 10-3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic

BASIC TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 10-4 NOTE:During a power-on reset operation, the CPU is idle during the required osc

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-1 11 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit time

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1-4 PIN ASSIGNMENT SEG0/P5.7COM0/P6.0COM1/P6.1COM2/P6.2COM3/P6.3VLC0VLC1VLC2VDDVSSX

TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11-2 Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to • Enab

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-3 NOTE:When one 16-bit timer mode (TACON.7 <- "1": Timer 1)TACON.6-.4MUX1/81/

TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11-4 TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit gen

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-5 TACON and TBCON are located in set 1, bank 1, at address E6H and E7H, and is read/write

TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11-6 Timer B Control Register (TBCON)E7H, Set 1, Bank 1, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBTi

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-7 NOTE:When two 8-bit timers mode (TACON.7 <- "0": Timer A)TACON.6-.4MUX1/81/

TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11-8 1/81/641/2561/512NOTE:When two 8-bit timers mode (TACON.7 <- "0": Timer B)T

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH TIMER 12-1 12 WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measu

WATCH TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 12-2 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH TIMER 12-3 WATCH TIMER CIRCUIT DIASGRAM WT INT EnableWTCON.1WTCON.2WTCON.3WTCON.4WTCON.5WTCON.6

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW 1-5 S3C8275X/F8275XS3C8278X/F8278XS3C8274X/F8274X(64-LQFP-1010)1234567891011121314151

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-1 13 LCD CONTROLLER/DRIVER OVERVIEW The S3C8275X/C8278X/C8274X microcontroll

LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 13-2 LCD CIRCUIT DIAGRAM Data BUSPortLatchLCONLCDDisplayRAM(200H-20FH)SEG/Por

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-3 LCD RAM ADDRESS AREA RAM addresses of page 2 are used as LCD data memory.

LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 13-4 LCD CONTROL REGISTER (LCON) A LCON is located in set 1, bank 1, at addre

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-5 LCD VOLTAGE DIVIDING RESISTOR NOTES:1. R = Internal LCD dividing resist

LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 13-6 COMMON (COM) SIGNALS The common signal output pin selection (COM pin sel

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-7 FRSelect Non-Select1 FrameCOMVssSEGVssCOM-SEGVssVLC1, 2VLC 0-VLC 0-VLC1, 2

LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 13-8 1 Frame012 312VSSVSSCOM0COM1COM3SEG0COM0-SEG0COM0-SEG1COM1-SEG1COM2FR03V

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SERIAL I/O INTERFACE 14-1 14 SERIAL I/O INTERFACE OVERVIEW Serial I/O modules, SIO can interface

SERIAL I/O INTERFACE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 14-2 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O inter

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1-6 PIN DESCRIPTIONS Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Des

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SERIAL I/O INTERFACE 14-3 SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O in

SERIAL I/O INTERFACE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 14-4 SERIAL I/O TIMING DIAGRAM (SIO) SOTransmitCompleteSIO INTSet SIOCON.3DO7

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BATTERY LEVEL DETECTOR 15-1 15 BATTERY LEVEL DETECTOR OVERVIEW The S3C8275X/C8278X/C8274X micro-co

BATTERY LEVEL DETECTOR S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 15-2 BATTERY LEVEL DETECTOR CONTROL REGISTER (BLDCON) The bit 3 of BLDCON

S3F8275X EMBEDDED FLASH MEMORY INTERFACE 16-1 16 EMBEDDED FLASH MEMORY INTERFACE OVERVIEW This chapter is only for the S3F8275X. The S3F8275X h

EMBEDDED FLASH MEMORY INTERFACE S3F8275X 16-2 USER PROGRAM MODE This mode supports sector erase, byte programming, byte read and one protectio

S3F8275X EMBEDDED FLASH MEMORY INTERFACE 16-3 Flash Memory User Programming Enable Register The FMUSR register is used for a safety operation of

EMBEDDED FLASH MEMORY INTERFACE S3F8275X 16-4 Flash Memory Sector Address Registers There are two sector address registers for addressing a se

S3F8275X EMBEDDED FLASH MEMORY INTERFACE 16-5 ISPTM (ON-BOARD PROGRAMMING) SECTOR ISPTM sectors located in program memory area can store on boar

EMBEDDED FLASH MEMORY INTERFACE S3F8275X 16-6 Table 16-1. ISP Sector Size Smart Option(003EH) ISP Size Selection BitBit 2 Bit 1 Bit 0 Area o

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW 1-7 Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions (Continue

S3F8275X EMBEDDED FLASH MEMORY INTERFACE 16-7 SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User P

EMBEDDED FLASH MEMORY INTERFACE S3F8275X 16-8 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Reg

S3F8275X EMBEDDED FLASH MEMORY INTERFACE 16-9 PROGRAMMING A flash memory is programmed in one byte unit after sector erase. And for programming

EMBEDDED FLASH MEMORY INTERFACE S3F8275X 16-10  PROGRAMMING TIP ⎯ Program • • SB1 LD FMUSR,#0A5H ; User Program mode enable LD FM

S3F8275X EMBEDDED FLASH MEMORY INTERFACE 16-11 READING The read operation of programming starts by 'LDC' instruction. The Reading Proc

EMBEDDED FLASH MEMORY INTERFACE S3F8275X 16-12 HARD LOCK PROTECTION User can set Hard Lock Protection by write ‘0110’ in FMCON.7−4. If this fu

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-1 17 ELECTRICAL DATA OVERVIEW In this chapter, S3C8275X/C8278X/C8274X electrical c

ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-2 Table 17-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Condition

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-3 Table 17-2. D.C. Electrical Characteristics (Continued) (TA = − 25°C to + 85

ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-4 Table 17-2. D.C. Electrical Characteristics (Concluded) (TA = − 25°C to +

NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea PRODUCT NAME: S3C8275X/F8275X/C8278X/F8278

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1-8 PIN CIRCUITS P-ChannelN-ChannelInVDD Figure 1-4. Pin Circuit Type A InVDDSchmit

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-5 Table 17-3. Data Retention Supply Voltage in Stop Mode (TA = − 25 °C to + 85

ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-6 Execution ofSTOP InstrctionRESETOccurs~~VDDDR~~Stop ModeOscillationStabilizati

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-7 Table 17-5. A.C. Electrical Characteristics (TA = − 25°C to + 85°C, VDD = 2.

ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-8 nRESETtRSL0.2 VDD Figure 17-4. Input Timing for RESET tKHtKL0.2VDDSCKtKCY0.8V

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-9 Table 17-6. Battery Level Detector Electrical Characteristics (TA = 25°C, VDD

ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-10 Table 17-8. Main Oscillation Characteristics (TA = − 25°C to + 85°C) Os

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-11 Table 17-10. Main Oscillation Stabilization Time (TA = − 25 °C to + 85 °C,

ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-12 Table 17-11. Sub Oscillation Stabilization Time (TA = − 25 °C to + 85 °C,

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-13 2 MHz6.25 kHz(main)/8.2 kHz(sub)24Supply Voltage (V)Instruction Clock = 1/4n x

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MECHANICAL DATA 18-1 18 MECHANICAL DATA OVERVIEW The S3C8275X/C8278X/C8274X microcontroller is currently

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW 1-9 OutCOM/SEGVLC0VLC1VLC2OutputDisableVSS Figure 1-7. Pin Circuit Type H-4 VDDOpen

MECHANICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 18-2 0.08 MAX0.09~0.2064-LQFP-1010#64NOTE: Dimensions are in millimeters.10.00 BSC12.

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU 19-1 19 S3F8275X/F8278X/F8274X FLASH MCU OVERVIEW The S3F8275X/F8

S3F8275X/F8278X/F8274X FLASH MCU S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 19-2 S3F8275XS3F8278XS3F8274X(64-QFP-1420F)123456789101112131415

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU 19-3 S3F8275XS3F8278XS3F8274X(64-LQFP-1010)12345678910111213141516

S3F8275X/F8278X/F8274X FLASH MCU S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 19-4 Table 19-1. Descriptions of Pins Used to Read/Write the Fla

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU 19-5 OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the

S3F8275X/F8278X/F8274X FLASH MCU S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 19-6 Table 19-4. D.C. Electrical Characteristics (TA = − 25°C

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU 19-7 2 MHz6.25 kHz (main)/8.2 kHz(sub)24Supply Voltage (V)Instruct

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS 20-1 20 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use devel

DEVELOPMENT TOOLS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 20-2 BUSSMDS2+RS-232CPODProbeAdapterPROM/OTP Writer UnitRAM Break/Display UnitTrac

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1-10 VDDDataOutputDisable 1COM/SEGOutputDisable 2Resistor EnableVDDCircuitType H-4P

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS 20-3 TB8275/8/4 TARGET BOARD The TB8275/8/4 target board is used for the S3C8275X/C82

DEVELOPMENT TOOLS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 20-4 Table 20-1. Power Selection Settings for TB8275/8/4 "To User_Vcc" S

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS 20-5 Table 20-3. Select Smart Option Source Setting for TB8275/8/4 "Smart Option

DEVELOPMENT TOOLS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 20-6 Table 20-5. Device Selection Settings for TB8275/8/4 "Device Selection&q

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS 20-7 INT7/P1.7SEG30/P2.1SEG28/P2.3SEG26/P2.5SEG24/P2.7SEG22/P3.1SEG20/P3.3SEG18/P3.5S

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW 1-11 VDDDataOutputDisable 1Resistor EnableVDDCircuitType H-4P-CHN-CHPull-UpResistorI/

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-1 2 ADDRESS SPACES OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has two types

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-3 SMART OPTION ROM Address: 003EHLSBMSB .7 .6 .5 .4 .3 .2 .1 .0ISP reset vector chang

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-4 Smart option is the ROM option for start condition of the chip. The ROM address u

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-5 REGISTER ARCHITECTURE In the S3C8275X/C8278X/C8274X implementation, the upper 64-by

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-6 System Registers(Register Addressing Mode)General Purpose Register(Register Addre

REVISION HISTORY Revision Date Remark 0 February, 2005 Preliminary spec for internal release only. 1 April, 2005 First edition. Reviewed by Finec

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-7 System Registers(Register Addressing Mode)General Purpose Register(Register Addres

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-8 REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expa

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-9  PROGRAMMING TIP — Using the Page Pointer for RAM Clear (Page 0, Page 1) LD PP,#0

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-10 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file,

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-11 PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3C8275X/C8278X/C8274X&a

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-12 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit reg

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-13 USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H a

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-14 16-ByteContiguousworkingRegister blockRegister FileContains 328-Byte Slices0 0

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-15 REGISTER ADDRESSING The S3C8-series register architecture provides an efficient me

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-16 RP1RP0RegisterPointers00HAllAddressingModesPage 0Indirect Register,IndexedAddres

REVISION DESCRIPTIONS 1. Electrical Data Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM (TA = − 25 °C to + 85 °C, VDD = 2.0

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-17 COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-18  PROGRAMMING TIP — Addressing the Common Working Register Area As the following

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-19 Together they create an8-bit register addressRegister pointerprovides fivehigh-ord

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-20 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addres

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-21 8-bit addressform instruction'LD R11, R2'RP00 1 1 0 0 0 0 01 1 0

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-22 SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 2-23  Programming TIP — Standard Stack Operations Using PUSH and POP The following exa

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES 3-1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are f

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-2 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES 3-3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode

Descriptions of Revision 1.4 1. Smart Option Area The Figures are modified about smart option area. Those are “Figure 2-1. Program Memory Address Sp

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-4 INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODEPAIRPoints toRegister Pa

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES 3-5 INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODEADDRESS4-bitWorkingRegist

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-6 INDIRECT REGISTER ADDRESSING MODE (Concluded) dstOPCODE4-bit WorkingRegister Ad

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES 3-7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-8 INDEXED ADDRESSING MODE (Continued) Register FileOPERANDProgram MemoryorData Me

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES 3-9 INDEXED ADDRESSING MODE (Concluded) Register FileOPERANDProgram MemoryorData Mem

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES 3-11 DIRECT ADDRESS MODE (Continued) OPCODEProgram MemoryLower Address ByteMemoryAdd

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-12 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction spec

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES 3-13 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement sig

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER iii Preface The S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Microcontroller User's

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-1 4 CONTROL REGISTERS OVERVIEW In this chapter, detailed descriptions of the S3C8

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-2 Table 4-2. Set 1, Bank 0 Registers Register Name Mnemonic Address R/W D

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-3 Table 4-3. Set 1, Bank 1 Registers Register Name Mnemonic Address R/W Deci

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-4 FLAGS - System Flags Register.7 Carry Flag (C).6 Zero Flag (Z).5Bit Identifi

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-5 BLDCON — Battery Level Detector Control Register F4H Set 1, Bank 1 Bit Identi

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-6 BTCON — Basic Timer Control Register D3H Set 1 Bit Identifier .7 .6 .5 .4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-7 CLKCON — System Clock Control Register D4H Set 1 Bit Identifier .7 .6 .5 .4

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-8 CLOCON — Clock Output Control Register E8H Set 1, Bank 1 Bit Identifier .

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-9 EXTICONH — External Interrupt Control Register (High Byte) F8H Set 1, Bank 0

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER v Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8-Series

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-10 EXTICONL — External Interrupt Control Register (Low Byte) F9H Set 1, Bank

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-11 EXTIPND — External Interrupt Pending Register F7H Set 1, Bank 0 Bit Identifi

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-12 FLAGS — System Flags Register D5H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-13 FMCON — Flash Memory Control Register F0H Set 1, Bank 1 Bit Identifier .7 .

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-14 FMSECH — Flash Memory Sector Address Register (High Byte) F2H Set 1, Bank

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-15 FMUSR — Flash Memory User Programming Enable Register F1H Set 1, Bank 1 Bit

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-16 IMR — Interrupt Mask Register DDH Set 1 Bit Identifier .7 .6 .5 .4 .3 .

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-17 IPH — Instruction Pointer (High Byte) DAH Set 1 Bit Identifier

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-18 IPR — Interrupt Priority Register FFH Set 1, Bank 0 Bit Identifier .7 .6

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-19 IRQ — Interrupt Request Register DCH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2

vi S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER Table of Contents (Continued) Chapter 4 Control Registers Overview...

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-20 LCON — LCD Control Register E0H Set 1, Bank 1 Bit Identifier .7 .6 .5 .

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-21 OSCCON — Oscillator Control Register E0H Set 1, Bank 0 Bit Identifier .7 .

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-22 P0CONH — Port 0 Control Register (High Byte) E4H Set 1, Bank 0 Bit Identi

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-23 P0CONL — Port 0 Control Register (Low Byte) E5H Set 1, Bank 0 Bit Identifier

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-24 P0PUR — Port 0 Pull-Up Control Register E6H Set 1, Bank 0 Bit Identifier

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-25 P1CONH — Port 1 Control Register (High Byte) E7H Set 1, Bank 0 Bit Identifie

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-26 P1CONL — Port 1 Control Register (Low Byte) E8H Set 1, Bank 0 Bit Identif

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-27 P1PUR — Port 1 Pull-up Control Register F9H Set 1, Bank 0 Bit Identifier .

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-28 P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 0 Bit Identi

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-29 P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 0 Bit Identifier