Samsung S3C8275X Manual do Utilizador Página 162
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INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
6-28
CLR — Clear
CLR dst
Operation: dst ← "0"
The destination location is cleared to "0".
Flags: No flags are affected.
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode
dst
opc dst 2 4 B0 R
4 B1 IR
Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR 00H → Register 00H = 00H
CLR @01H → Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H
value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)
addressing mode to clear the 02H register value to 00H.
- S3C8275X/F8275X/C8278X 1
- /F8278X/C8274X/F8274X 1
- Important Notice 2
- NOTIFICATION OF REVISIONS 3
- REVISION HISTORY 4
- REVISION DESCRIPTIONS 5
- Descriptions of Revision 1.4 6
- Preface 7
- Table of Contents 8
- Chapter 6 Instruction Set 9
- Chapter 7 Clock Circuit 10
- Chapter 9 I/O Ports 10
- Chapter 10 Basic Timer 10
- Chapter 11 Timer 1 11
- Chapter 12 Watch Timer 11
- List of Figures 13
- List of Figures (Continued) 15
- List of Figures (Concluded) 16
- List of Tables 17
- List of Tables (Continued) 18
- List of Programming Tips 19
- (Continued) 22
- 1 PRODUCT OVERVIEW 23
- FEATURES 24
- BLOCK DIAGRAM 25
- (64-QFP-1420F) 26
- S3C8275X/F8275X 27
- S3C8278X/F8278X 27
- S3C8274X/F8274X 27
- PIN DESCRIPTIONS 28
- PIN CIRCUITS 30
- – P2.7, P3) 31
- 2 ADDRESS SPACES 34
- PROGRAM MEMORY (ROM) 35
- SMART OPTION 36
- Figure 2-2. Smart Option 36
- REGISTER ARCHITECTURE 38
- REGISTER ADDRESSING 48
- SYSTEM AND USER STACK 55
- 3 ADDRESSING MODES 57
- REGISTER ADDRESSING MODE (R) 58
- (Concluded) 62
- INDEXED ADDRESSING MODE (X) 63
- DIRECT ADDRESS MODE (DA) 66
- INDIRECT ADDRESS MODE (IA) 68
- RELATIVE ADDRESS MODE (RA) 69
- IMMEDIATE MODE (IM) 70
- 4 CONTROL REGISTERS 71
- FLAGS - System Flags Register 74
- 4-10 80
- 4-11 81
- 4-12 82
- 4-13 83
- 4-14 84
- 4-15 85
- 4-16 86
- 4-17 87
- 4-18 88
- 4-19 89
- 4-22 92
- 4-23 93
- 4-24 94
- 4-25 95
- 4-26 96
- 4-27 97
- 4-28 98
- 4-29 99
- 4-30 100
- or alternative function 100
- 4-31 101
- 4-32 102
- 4-33 103
- 4-34 104
- 4-35 105
- 4-36 106
- 4-37 107
- 4-38 108
- 4-40 110
- 4-41 111
- 4-42 112
- 4-43 113
- 4-45 115
- 4-46 116
- 4-47 117
- 5 INTERRUPT STRUCTURE 118
- 5-10 127
- 5-11 128
- 5-12 129
- 5-13 130
- 5-14 131
- 5-15 132
- 5-16 133
- 5-17 134
- 6 INSTRUCTION SET 135
- 6-10 144
- ↓ ↓ ↓ ↓ ↓ ↓ ↓ 145
- 6-13 147
- ADC — Add with carry 148
- ADD — Add 149
- — Logical AND 150
- — Bit AND 151
- BCP — Bit Compare 152
- — Bit Complement 153
- BITR — Bit Reset 154
- BITS — Bit Set 155
- BOR — Bit OR 156
- BXOR — Bit XOR 159
- CALL — Call Procedure 160
- CCF — Complement Carry Flag 161
- CLR — Clear 162
- COM — Complement 163
- CP — Compare 164
- 6-31 165
- 6-32 166
- DA — Decimal Adjust 167
- DEC — Decrement 169
- DECW — Decrement Word 170
- DI — Disable Interrupts 171
- DIV — Divide (Unsigned) 172
- 6-39 173
- EI — Enable Interrupts 174
- ENTER — Enter 175
- EXIT — Exit 176
- IDLE — Idle Operation 177
- INC — Increment 178
- INCW — Increment Word 179
- Interrupt Return 180
- JP — Jump 181
- JR — Jump Relative 182
- LD — Load 183
- LDB — Load Bit 185
- LDC/LDE — Load Memory 186
- Load Memory and Decrement 188
- Load Memory and Increment 189
- 6-56 190
- 6-57 191
- LDW — Load Word 192
- MULT — Multiply (Unsigned) 193
- NEXT — Next 194
- NOP — No Operation 195
- OR — Logical OR 196
- POP — Pop From Stack 197
- 6-64 198
- 6-65 199
- PUSH — Push To Stack 200
- 6-67 201
- 6-68 202
- RCF — Reset Carry Flag 203
- RET — Return 204
- RL — Rotate Left 205
- Rotate Left Through Carry 206
- RR — Rotate Right 207
- Rotate Right Through Carry 208
- SB0 — Select Bank 0 209
- SB1 — Select Bank 1 210
- SBC — Subtract with Carry 211
- SCF — Set Carry Flag 212
- SRA — Shift Right Arithmetic 213
- Set Register Pointer 214
- STOP — Stop Operation 215
- SUB — Subtract 216
- SWAP — Swap Nibbles 217
- Test Complement Under Mask 218
- TM — Test Under Mask 219
- WFI — Wait for Interrupt 220
- XOR — Logical Exclusive OR 221
- 7 CLOCK CIRCUIT 222
- 32.768 kHz 223
- 8 RESET and POWER-DOWN 230
- POWER-DOWN MODES 234
- 9 I/O PORTS 236
- .7 .6 .5 .4 .3 .2 .1 .0 LSB 237
- 9-3 238
- 9-5 240
- 9-7 242
- 9-9 244
- 9-15 250
- 9-19 254
- 10 BASIC TIMER 255
- 10-3 257
- 10-4 258
- 11 TIMER 1 259
- 12 WATCH TIMER 267
- WATCH TIMER CIRCUIT DIASGRAM 269
- 13 LCD CONTROLLER/DRIVER 270
- LCD CIRCUIT DIAGRAM 271
- LC0, VLC1(VLC2), and VSS 273
- S3C8275X/C8278X/C8274X 274
- 14 SERIAL I/O INTERFACE 278
- 14-2 279
- SIO BLOCK DIAGRAM 280
- 14-4 281
- BATTERY LEVEL DETECTOR 282
- 283
- OVERVIEW 284
- USER PROGRAM MODE 285
- 16-3 286
- S3F8275X 288
- SECTOR ERASE 290
- 16-8 291
- PROGRAMMING 292
- PROGRAMMING TIP ⎯ Program 293
- PROGRAMMING TIP ⎯ Reading 294
- HARD LOCK PROTECTION 295
- 17 ELECTRICAL DATA 296
- 0 V) 301
- 17-11 306
- 17-12 307
- 18 MECHANICAL DATA 309
- 64-LQFP-1010 310
- version of the 311
- S3F8278X 312
- S3F8274X 312
- 19-3 313
- 19-7 317
- 20 DEVELOPMENT TOOLS 318
- 20-2 319
- TB8275/8/4 320
- To User_V 321
- Internal External 322
- Select Smart 322
- Option Source 322
- S3F8278/4 S3F8275 323
- Device Selection 323
- 40-Pin DIP Connector 324
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